MC68HC908AP16CFB datasheet(160/440 Pages) MOTOROLA

160 / 440 page

Monitor ROM (MON)

Data Sheet

MC68HC908AP Family — Rev. 2.5

160

MOTOROLA

10.3.2 Data Format

Communication with the monitor ROM is in standard non-return-to-zero

(NRZ) mark/space data format. Transmit and receive baud rates must

be identical.

Figure 10-3. Monitor Data Format

10.3.3 Break Signal

A start bit (logic 0) followed by nine logic 0 bits is a break signal. When

the monitor receives a break signal, it drives the PTA0 pin high for the

duration of two bits and then echoes back the break signal.

Figure 10-4. Break Transaction

10.3.4 Baud Rate

The communication baud rate is controlled by the crystal frequency and

the state of the PTB0 pin (when IRQ1 is set to VTST) upon entry into

monitor mode. When PTB0 is high, the divide by ratio is 1024. If the

PTB0 pin is at logic 0 upon entry into monitor mode, the divide by ratio

is 512.

If monitor mode was entered with VDD on IRQ1, then the divide by ratio

is set at 1024, regardless of PTB0. If monitor mode was entered with VSS

on IRQ1, then the internal PLL steps up the external frequency,

presumed to be 32.768 kHz, to 2.4576 MHz. These latter two conditions

for monitor mode entry require that the reset vector is blank.

BIT 5

START

BIT

BIT 0

BIT 1

STOP

BIT

START

BIT

BIT 2

BIT 3

BIT 4

BIT 6

BIT 7

MISSING STOP BIT

2-STOP BIT DELAY BEFORE ZERO ECHO

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB Datasheet(PDF) 160 Page - Motorola, Inc

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