7643 datasheet(181/424 Pages) RENESAS

181 / 424 page

Rev.2.00

Aug 28, 2006

page 60 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.4 UART

Fig. 2.4.24 Connection diagram

(3) Data packet transfer (with no error processing) from USB FIFO to UART using DMA

Outline : transmit the data in USB FIFO to Host CPU using DMA and UART.

Specifications : • USB Endpoint1: OUT bulk transfer

• USB Endpoint1: OUT interrupt

• USB Endpoint1 packet size: 64 Bytes

• UART transmit is used.

• DMA cycle steal transfer mode (fixed address -> fixed address transfer)

• DMA transfer unit : 64 bytes fixed (short packet un-supported)

• UART transmit interrupt request (when transmitting shift operation is completed)

is used for DMA factor

• Transfer bit rate : 9600 bps (

φ = 12 MHz divided by 1248)

In this case, f(XIN)=24 MHz, system clock=f(XIN).

φ is system clock divided by 2.

• Data format: 1ST-8DATA-1SP

• Parity bit is disabled

• Re-transmit by transfer error is not performed

• Use of CTS functions

The UART transmit is enabled by USB Endpoint1 OUT interrupt after USB data is received from

the host PC. The UART transmit interrupt source is set for a trigger of DMA.

The first UART transmit interrupt source (UART transmit interrupt is not used) occurs by enable

of UART transmit. By this UART transmit interrupt as a trigger of DMA, the data of USB FIFO is

transmitted to the UART transmit/receive buffer register.

In the 7643 group, DMA interrupt occurs after DMA transmits the 64-byte data of USB FIFO to

UART. In this time, the UART transmit is disabled and the OUT_PKT_RDY flag of USB Endpoint1

OUT is cleared to “0.” As a result, the USB Endpoint1 can receive the following data.

Figure 2.4.24 shows a connection diagram.

Figure 2.4.25, 2.4.26 and 2.4.27 show register settings.

Figure 2.4.28 and 2.4.29 show control procedures.

URXD

RTS

P84/UTXD

P86/CTS

7643 Group

Host CPU

USB

DMA transfer

USB OUT

Host PC

Transmitting side

Receiving side

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