7643 datasheet(179/424 Pages) RENESAS

179 / 424 page

Rev.2.00

Aug 28, 2006

page 58 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.4 UART

Fig. 2.4.22 Control procedure (1)

P3 (Address : 0E16), bit1?

UCON (Address : 3316)

010x10002

010x10102

• Countermeasure for a bit slippage

UCON (Address : 3316), bit1

• Reception starts.

RESET

Initialization

q x: This bit is not used here. Set it to “0” or “1” arbitrarily.

CLI

•

φ as UART clock, 2 stop bits,

Parity checking disabled, 8-bit character length

• Port P31 to input mode

• UART receive buffer full interrupt enabled

• UART summing error interrupt enabled

(Address : 3116)

(Address : 3316)

(Address : 3016)

(Address : 0F16), bit1

(Address : 0516), bit6

(Address : 0616), bit0

UBRG

UCON

UMOD

P3D

ICONA

ICONB

4D16

100x11102

010x10002

Main process

RTI

Note 1: When using Index X mode flag (T)

Note 2: When using Decimal mode flag (D)

•Push registers used in interrupt process routine

Pop registers

CLT (Note 1)

CLD (Note 2)

Push registers to stack

UART summing error interrupt routine

Error process

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