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7643 Datasheet(PDF) 180 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 180 Page - Renesas Technology Corp |
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180 / 424 page  Rev.2.00 Aug 28, 2006 page 59 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.4 UART Fig. 2.4.23 Control procedure (2) Low-order 7 bits of received data = 0216? UCON (Address : 3316), bit7 • Address mode enabled UART receive buffer full interrupt routine q x: This bit is not used here. Set it to “0” or “1” arbitrarily. RTI Note 1: When using Index X mode flag (T) Note 2: When using Decimal mode flag (D) •Push registers used in interrupt process routine Pop registers CLT (Note 1) CLD (Note 2) Push registers to stack No : Address other than Slave CPU (B)’s Slave CPU (B) receiving side MSB of received data? 1 0 : Data reception Store received data • Data reception Receive buffer full flag is set to “0” by reading data. Read out a received data from UTRB1 (Address : 3416) 1 : Address reception Yes : Address of Slave CPU (B) |
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