DP83266 datasheet(3/152 Pages) NSC

3 / 152 page

10 FDDI Chip Set Overview

National Semiconductor’s FDDI chip set is shown in

Figure

1-1 For more information about the PLAYERaTM device

consult the appropriate datasheet and application notes

DP8325656-AP57 PLAYERa

Device Physical Layer Controller

The PLAYERa device implements the Physical Layer

(PHY) protocol as defined by the ANSI FDDI PHY X3T95

Standard along with all the necessary clock recovery and

clock generation functions

Features

Single chip FDDI Physical Layer (PHY) solution

Integrated Digital Clock Recovery Module provides en-

hanced tracking and greater lock acquisition range

Integrated Clock Generation Module provides all neces-

sary clock signals for an FDDI system from an external

125 MHz reference

Alternate PMD Interface (DP83256-AP57) Supports

UTP twisted pair FDDI PMDS with no external clock re-

covery or clock generations functions required

No External Filter Components

Connection Management (CMT) Support (LEM TNE

React CF

React Auto Scrubbing)

Full on-chip configuration switch

Low Power CMOS-BIPOLAR design using a single 5V

supply

Full duplex operation with through parity

Separate management interface (Control Bus)

Selectable Parity on PHY-MAC Interface and Control Bus

Interface

Two levels of on-chip loopback

4B5B encoderdecoder

Framing logic

Elasticity Buffer Repeat Filter and Smoother

Line state detectorgenerator

Supports single attach stations dual attach stations and

concentrators with no external logic

DP8325656-AP for SASDAS single path stations

DP83257 for SASDAS singledual path stations

addition

the

DP83257

contains

additional

PHY

Datarequest and PHY

Dataindicate port required

for concentrators and dual attach stations

DP83266 MACSI Device

Media Access Controller and

System Interface

The MACSI device implements the Timed Token Media Ac-

cess Control protocol defined by the ANSI FDDI X3T95

MAC Standard as well as a high performance system inter-

face

Features

Over 9 kBytes of on-chip FIFO

5 DMA channels (2 Output and 3 Input)

125 MHz to 25 MHz operation

Full duplex operation with through parity

Supports JTAG boundary scan

Real-time Void stripping indicator for bridges

On-chip address bit swapping capability

32-bit wide AddressData path with byte parity

Programmable transfer burst sizes of 4 or 8 32-bit words

Receive frame filtering services

Frame-per-Page mode controllable on each

DMA channel

Demultiplexed Addresses supported on ABus

New multicast address matching feature

ANSI X3T95 MAC standard defined ring service options

Supports all FDDI Ring Scheduling Classes

(Synchronous Asynchronous etc)

Supports Individual Group Short Long and

External Addressing

Generates Beacon Claim and Void frames

Extensive ring and station statistics gathering

Extensions for MAC level bridging

Enhanced SBus compatibility

Interfaces to DRAMs or directly to system bus

Supports frame HeaderInfo splitting

Programmable Big or Little Endian alignment

DP83266 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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