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DP83266 Datasheet(PDF) 70 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 70 Page - National Semiconductor (TI) |
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70 / 152 page  70 Control Information (Continued) Internal Event Latch Register (IELR) The Internal Event Latch Register (IELR) reports internal errors in the Ring Engine These errors include MAC Parity errors and inconsistencies in the Receiver and Transmitter state machines After an internal state machine error is detected and reported (bit RSMERR for the receiver and TSMERR for the transmitter) the Current Receive Status Register (CRS0) and Current Transmit Status Register (CTS0) continue to be updated as normal In Diagnose mode (ModeDiag e 1) the Current Receive Status Register and Current Transmit Status Register are frozen with the errored state until the internal state machine error condition is cleared (bit RSMERR andor TSMERR is set to Zero) Errors internal to the Ring Engine cause a MAC Reset Access Rules Address Read Write 028h Always Conditional Register Bits D7 D6 D5 D4 D3 D2 D1 D0 RES RES RES RES TSM ERR RSM ERR RES MPE Bit Symbol Description D7 – D4 RES Reserved D3 TSMERR Transmit State Machine Error Indicates inconsistency in the Transmitter state machine When set causes bit MCRST of the Function Register to be set D2 RSMERR Receive State Machine Error Indicates inconsistency in the Receiver state machine When set causes bit MCRST of the Function Register to be set D1 RES Reserved D0 MPE MAC Interface Parity Error Indicates a Parity Error on the MAC Request Data bus (the internal bus MRD (70) between the SI and MAC blocks) when parity is enabled on the MA Request Interface (bits MRP of the MAC Mode Register 0 (MCMR0)) are set and pin TXACK is asserted) 70 |
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