DP83266 datasheet(52/152 Pages) NSC

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70 Control Information (Continued)

The MACSI device has two interrupts signals One provides

interrupts on those events generated by the MAC state ma-

chines (INT0) and the other provides interrupts on those

events generated by the System Interface state machines

(INT1) This partition maintains hardware and software com-

patibility with earlier designs based on the BMAC and BSI

devices

At the first level of the hierarchy events are recorded as bits

in the Attention Registers (eg No Space Attention Regis-

ter) Each Attention Register has a corresponding Notify

Attention Register is set to One and its corresponding bit in

the Notify Register is also set to One the corresponding bit

in the Master Attention Register will be set to one

At the second level of the hierarchy if a bit in the Master

Attention Register is set to One and the corresponding bit in

the Master Notify Register is set to One the Interrupt signal

is asserted

To ensure that events are not missed when updating the

attention registers all attention registers are conditional

write registers Bits in Conditional Write Registers (eg No

Space Attention Register) are only written when the corre-

sponding bits in the Compare Register are equal to the bits

to be overwritten Read operations for conditional write reg-

isters automatically cause the Compare Register to be load-

ed with the contents of the conditional write register being

accessed The MACSI device contains two compare regis-

ters One is used for Ring Engine Event Registers (MCCMP)

and the other is used for System Interface Event Registers

(SICMP)

Events are recorded in Attention Registers and contribute to

the Interrupt when the bit in the corresponding Notify Regis-

ter is set (see

Figure 7-1 ) Bits in the Master Attention Reg-

ister (MAR) are not cleared directly They are cleared by

clearing the lower level attention andor notify register

The Event Registers include the following registers

Ring Engine Event Registers (INT0)

MAC Compare Register (MCCMP)

Current Receiver Status Register (CRS0)

Current Transmitter Status Register (CTS0)

Ring Event Latch Registers (RELR0 – 1)

Ring Event Mask Registers (REMR0 – 1)

Token and Timer Event Latch Register (TELR0)

Token and Timer Event Mask Register (TEMR0)

Counter Increment Latch Register (CILR)

Counter Increment Mask Register (CIMR)

Counter Overflow Latch Register (COLR)

Counter Overflow Mask Register (COMR)

Internal Event Latch Register (IELR)

Exception Status Register (ESR)

Exception Mask Register (EMR)

Interrupt Condition Register (ICR)

Interrupt Mask Register (IMR)

Service Engine Event Registers (INT1)

Master Attention Register (MAR)

Master Notify Register (MNR)

State Attention Register (STAR)

State Notify Register (STNR)

Service Attention Register (SAR)

Service Notify Register (SNR)

No Space Attention Register (NSAR)

No Space Notify Register (NSNR)

Request Attention Register (RAR)

Request Notify Register (RNR)

Indicate Attention Register (IAR)

Indicate Notify Register (INR)

System Interface Compare Register (SICMP)

Servicing Interrupts

In the process of servicing an interrupt the Host may use

one or both levels of condition masks to disable new inter-

rupts while one is being serviced Soon after the Manage-

ment Entity has processed the interrupt to some extent it is

ready to re-arm the interrupt in order to be notified of the

next condition

The Interrupt Control Register always contains the merged

output of the masked Condition Registers as shown in

Fig-

ure 7-1 It is only possible to remove a condition by setting

the corresponding Condition Latch Register bit to Zero By

storing the events on-chip and having the ability to selec-

tively set bits to Zero the need for the software to maintain

a copy of the Event Registers is eliminated

To prevent the overwriting and consequent missing of

events an interlock mechanism is used In the period be-

tween the Read of a Condition Latch Register and the cor-

responding Write to reset the condition additional events

can occur

In order to prevent software from overwriting bits which

have changed since the last read and losing interrupt

events a conditional write mechanism is employed Only

bits that have not changed since the last read can be written

to a new value

Whenever a Condition Latch Register is read its contents

are stored in the Compare Register There is one Compare

pare Register for the Service Engine Event Registers Each

bit of the Compare Register is compared with the current

contents of the Register that is to be written Writing a bit

with a new value to a Condition Register is only possible

when the corresponding bit in the Compare Register

matches the bit in the Condition Register For any bit that

has not changed the new value of the bit is written into the

is inhibited The fact that an attempt was made to change a

modified bit in the Register is latched in the Condition Write

Inhibit bit in the Exception Status Register (ESRCWI) for

Ring Engine Registers and in the State Attention Register

(STARCWI) for Service Engine Registers

In the MACSI device two Compare Registers are shared by

all of the Condition Latch Registers (In the PLAYERa de-

vice there is a Compare Register for every Event Register)

For the cases where more than one register must be read

before writing a new value the software may write the ap-

propriate Compare Register with the most recently read val-

ue before writing the register again Alternatively the Event

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