DP83266 datasheet(71/152 Pages) NSC

71 / 152 page

70 Control Information (Continued)

Exception Status Register (ESR)

The Exception Status Register (ESR) reports errors to the software Errors include PHY Interface Parity Errors illegal attempts

to access currently inaccessible registers and writing to a conditional write location if a register bit has changed since it was last

read Each bit may be masked via the Exception Mask Register (EMR)

Access Rules

Address

Read

Write

02Ch

Always

Conditional

CWI

CCE

CPE

RES

PPE

Bit

Symbol

Description

CWI

Conditional Write Inhibit

Indicates that at least one bit of the previous conditional write operation was

not written This bit is set unconditionally after each write to a conditional write register if the value of the

Compare Register is not equal to the value of the register that was accessed for a write before it was

written This may indicate that the accessed register has changed since it was last read

This bit is cleared after a successful conditional write This occurs when the value of the Compare

CWI does not contribute to setting the ESE bit of the Interrupt Condition Register (it is always implicitly

masked)

CCE

Control Bus Command Error

Indicates that a Control Bus command was not performed due to an error

ie illegal command or a Control Bus Write Parity Error An illegal command is an attempt to access a

currently inaccessible register

CPE

Control Bus Parity Error

Indicates a Control Bus Parity Error was detected on the Control Bus Data pins

(CBD7 – 0) during a write operation to a register Parity errors are reported if parity is enabled on the

Control Bus Interface (bit CBP of the Mode Register is set)

D4 – D1

RES

Reserved

PPE

PHY Interface Parity Error

Indicates parity error detected on PID7 – 0 Parity errors are reported when

parity is enabled on the PHY

Request Interface (bit PIP of the Mode Register is set)

DP83266 Datasheet(PDF) 71 Page - National Semiconductor (TI)

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