DP83266 datasheet(7/152 Pages) NSC

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30 Architectural Description (Continued)

31 INTERFACES

311 PHY Interface

The PHY Interface is a synchronous interface that provides

a byte stream to the PLAYERa device (the PHY Request

byte stream PHY

Request) and receives a byte stream

from the PLAYERa device (the PHY Indicate byte stream

PHY

Indicate)

The 10 bits transferred in both directions across the

Indicate and PH

Request Interfaces consists of one

parity bit (odd parity) one control bit and 8 bits of data The

control bit determines if the 8 data bits are a data symbol

pair or a control symbol pair

312 ABus Interface

The ABus interface provides the high performance synchro-

nous Data and Control interface to the Host System andor

local memory Data and Descriptors are transferred via this

interface over the 32-bit Data bus (with byte parity) Both

multiplexed and non-multiplexed address information is

available on this bus Arbitration and transfer control signals

are provided and minimize the requirements for external

glue logic

313 Control Bus Interface

The Control Interface implements the interface to the Con-

trol Bus which allows the user to initialize monitor and diag-

nose the operation of the MACSI The Control Interface is

an 8-bit interface This reduces the pinout and minimizes

board space All information that must be synchronized with

the data stream crosses the ABus Interface

The Control Bus is separated completely from the high per-

formance data path in order to allow independent operation

of the processor on the Control Bus The Control Interface

provides synchronization between the asynchronous Con-

trol Bus and the synchronous operation of the device

During operation the host uses the Control Bus to access

the device’s internal registers and to manage the attention

notify (interrupt) logic

32 RING ENGINE

The Ring Engine consists of four blocks Receiver Trans-

mitter

MAC Parameter RAM

and CountersTimers as

shown in

Figure 3-2

321 Receiver

The Receiver accepts data from the PHY level device in

byte stream format (PH

Indicate)

Upon receiving the data the Receiver performs the follow-

ing functions

Determines the beginning and ending of a Protocol Data

Unit (PDU)

Decodes the Frame Control field to determine the PDU

type (frame or token)

Compares the received Destination and Source Address-

es with the internal addresses

Processes data within the frame

Calculates and checks the Frame Check Sequence at

the end of the frame

Checks the Frame Status field

And finally the Receiver presents the data to the MAC Inter-

face

along

with

the

appropriate

control

signals

(MA

Indicate)

322 Transmitter

The Transmitter inserts frames from this station into the ring

in accordance with the FDDI Timed-Token MAC protocol It

also repeats frames from other stations in the ring The

Transmitter block multiplexes data from the MA

Request

Interface and data from the Receiver Block During frame

transmission data from the Request Interface is selected

During frame repeating data from the Receiver is selected

TLF11705 – 3

FIGURE 3-2 Ring Engine Block Diagram

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