DP83266 datasheet(51/152 Pages) NSC

51 / 152 page

70 Control Information (Continued)

Control Registers

The Control Registers are used to configure and control the

operation of the MACSI device

The Control Registers include the following registers

MAC Mode Registers (MCMR2–0) establish the major

operating parameters for the MAC portion of the MACSI

device

Option Register (Option) selects major configuration

options for the MAC portion of the device

Function Register (Function) initiates major MAC level

functions

MAC Revision (MCRev) this register contains the silicon

revision code for the MAC state machines of this device

System Interface Mode Registers (SIMR1–0) estab-

lishes major operating parameters for the System Inter-

face

Pointer RAM Control and Address Register (PCAR) is

used to program the parameters for the PTOP (Pointer

RAM Operation) service function

Mailbox Address Register (MBAR) is used to program

the memory address of the mailbox used in the data

transfer of the PTOP service function

Limit Address Register (LAR) is used to program the

parameters and data used in the LMOP (Limit RAM Op-

eration) service function

Limit Data Register (LDR) is used to program the data

used in the LMOP service function

Request Channel 0 Configuration Registers (R0CR1–

are used to program the operational parameters for

Request Channel 0

Request Channel 1 Configuration Registers (R1CR1–

are used to program the operational parameters for

Request Channel 1

Request Channel 0 Expected Frame Status Register

(R0EFSR)

defines the expected frame status for frames

being confirmed on Request Channel 0

Request Channel 1 Expected Frame Status Register

(R1EFSR)

defines the expected frame status for frames

being confirmed on Request Channel 1

Indicate Threshold Register (ITR) is used to specify a

maximum number of frames that can be copied onto an

Indicate Channel before a breakpoint is generated

Indicate Mode Configuration Register (IMCR) speci-

fies how the incoming frames are sorted onto Indicate

Channels enables frame filtering and enables break-

points on various burst boundaries

Indicate Copy Configuration Register (ICCR) is used

to program the copy criteria for each of the Indicate

Channels

Indicate Header Length Register (IHLR) defines the

length of the frame header for use with the HeaderInfo

Sort Mode

Event Registers

The Event Registers record the occurrence of events or

series of events Events are recorded and contribute to gen-

erating Interrupt signals There is a two-level hierarchy in

generating this signal as shown in

Figure 7-1

TLF11705 – 17

FIGURE 7-1 Event Registers Hierarchy

DP83266 Datasheet(PDF) 51 Page - National Semiconductor (TI)

DP83266 Datasheet(HTML) 51 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL