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DP83266 Datasheet(PDF) 44 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 44 Page - National Semiconductor (TI) |
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44 / 152 page  70 Control Information (Continued) TABLE 7-1 MACSI Memory Map (BMAC Registers) (Continued) Address Register Name Access Rules Reset Value Read Write 028 Internal Event Latch Register (IELR) Always Conditional 00 029 – 02B Reserved NA NA 02C Exception Status Register (ESR) Always Conditional 00 02D Exception Mask Register (EMR) Always Always 00 02E Interrupt Condition Register (ICR) Always Data Ignored 00 02F Interrupt Mask Register (IMR) Always Always 00 030 – 03F Reserved NA NA 040 – 07F MAC Parameters Stop Mode Stop Mode NA 080 – 0BF CountersTimers Always Stop Mode NA 0C0-0FF Reserved NA NA e Contains a MAC Revision code NA e Not altered upon reset NA e Not Applicable Table 7-2 MACSI Memory Map (BSI Registers) Address Register Name Access Rules Reset Value Read Write 100 System Interface Mode Register 0 (SIMR0) Always Always 00 101 System Interface Mode Register 1 (SIMR1) Always Always 00 102 Pointer RAM Control and Address Register (PCAR) Always Always NA 103 Mailbox Address Register (MBAR) Always Always 104 Master Attention Register (MAR) Always Data Ignored 00 105 Master Notify Register (MNR) Always Always 00 106 State Attention Register (STAR) Always Conditional 07 107 State Notify Register (STNR) Always Always 00 108 Service Attention Register (SAR) Always Conditional 0F 109 Service Notify Register (SNR) Always Always 00 10A No Space Attention Register (NSAR) Always Conditional FF 10B No Space Notify Register (NSNR) Always Always 00 10C Limit Address Register (LAR) Always Always NA 10D Limit Data Register (LDR) Always Always NA 10E Request Attention Register (RAR) Always Conditional 00 10F Request Notify Register (RNR) Always Always 00 110 Request Channel 0 Configuration Register 0 (R0CR0) Always Always NA 111 Request Channel 1 Configuration Register 0 (R1CR0) Always Always NA 112 Request Channel 0 Expected Frame Status Register (R0EFSR) Always Always NA 113 Request Channel 1 Expected Frame Status Register (R1EFSR) Always Always NA 44 |
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