DP83266 datasheet(98/152 Pages) NSC

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70 Control Information (Continued)

No Space Attention Register (NSAR)

The No Space Attention Register (NSAR) presents the attentions generated when the CNF PSP or IDUD Queues run out of

space The host may set any attention bit to cause an attention for test purposes only though this should not be done during

normal operation

The No Data Space attentions are set and cleared by the MACSI device automatically The No Status Space attentions are set

by the MACSI device and must be cleared by the host

Upon reset this register is set to 0xff

Access Rules

Address

Read

Write

10Ah

Always

Conditional

NSR0

NSR1

LDI0

NSI0

LDI1

NSI1

LDI2

NSI2

Bit

Symbol

Description

NSI2

No Status Space on ICHN2

This bit is set by the MACSI device upon a Reset or when an IDUD has been

written to the next-to-last available entry in the Indicate Channel’s IDUD Status Queue When this occurs the

MACSI device stops copying on ICHN2 and the last IDUD is written with special status This bit must be

cleared by the host before the MACSI device will resume copying on this Channel Note that this bit should

only be cleared after the appropriate limit register has been updated to give the MACSI more status space

LDI2

Low Data Space on ICHN2

This bit is set by the MACSI device upon Reset or when a PSP is prefetched

from ICHN2’s last PSP Queue location (as defined by the PSP Queue Limit Register) Note that the amount of

warning is dependent on the length of the frame There will always be one more page (4 kBytes) available for

the MACSI device when this attention is generated Another FDDI maximum-length frame (after the current

one) will not fit in this space If PSP fetching was stopped because there were no more PSP entries fetching

will resume automatically when the PSP Queue Limit Register is updated This bit will be cleared automatically

when the new PSP Descriptors are fetched This bit should never be cleared directly by software Clearing this

bit can cause the MACSI device to fetch invalid PSP descriptors

NSI1

No Status Space on ICHN1

This bit is set by the MACSI device upon a Reset or when an IDUD has been

written to the next-to-last available entry in the Indicate Channel’s IDUD Status Queue When this occurs the

MACSI device stops copying on ICHN1 and the last IDUD is written with special status This bit must be

cleared by the host before the MACSI device will resume copying on this Channel Note that this bit should

only be cleared after the appropriate limit register has been updated to give the MACSI device more status

space

LDI1

Low Data Space on ICHN1

This bit is set by the MACSI device upon Reset or when a PSP is prefetched

from ICHN1’s last PSP Queue location (as defined by the PSP Queue Limit Register) Note that the amount of

warning is dependent on the length of the frame There will always be one more page (4 kBytes) available for

the MACSI device when this attention is generated Another FDDI maximum-length frame (after the current

one) will not fit in this space If PSP fetching was stopped because there were no more PSP entries fetching

will resume automatically when the PSP Queue Limit Register is updated This bit will be cleared automatically

when the new PSP Descriptors are fetched This bit should never be cleared directly by software Clearing this

bit can cause the MACSI device to fetch invalid PSP descriptors

DP83266 Datasheet(PDF) 98 Page - National Semiconductor (TI)

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