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DP83266 Datasheet(PDF) 93 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 93 Page - National Semiconductor (TI) |
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93 / 152 page  70 Control Information (Continued) Master Attention Register (MAR) The Master Attention Register (MAR) collects enabled attentions from the State Attention Register Service Attention Register No Space Attention Register Request Attention Register and Indicate Attention Register If the Notify bit in the Master Notify Register and the corresponding bit in the MAR are set to One the INT1 pin is forced to LOW and thus triggers an interrupt Writes to the Master Attention Register are permitted but do not change the contents All bits in this register are set to Zero upon reset Access Rules Address Read Write 104h Always Data Ignored Register Bits D7 D6 D5 D4 D3 D2 D1 D0 STA NSA SVA RQA INA RES RES RES Bit Symbol Description D2 – D0 RES Reserved D3 INA Indicate Attention Register Is set if any bit in the Indicate Attention Register is set D4 RQA Request Attention Register Is set if any bit in the Request Attention Register is set D5 SVA Service Attention Register Is set if any bit in the Service Attention Register is set D6 NSA No Space Attention Register Is set if any bit in the No Space Attention Register is set D7 STA State Attention Register Is set if any bit in the State Attention Register is set Master Notify Register (MNR) The Master Notify Register (MNR) is used to enable attentions in the Master Attention Register (MAR) If a bit in Register MNR and the corresponding bit in Register MAR are set to One the INT1 signal is asserted to cause an interrupt All bits in this register are set to Zero upon reset Access Rules Address Read Write 105h Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 STAN NSAN SVAN RQAN INAN RES RES RES Bit Symbol Description D2 – D0 RES Reserved D3 INAN Indicate Attention Register Notify This bit is used to enable the INA bit in Register MAR D4 RQAN Request Attention Register Notify This bit is used to enable the RQA bit in Register MAR D5 SVAN Service Attention Register Notify This bit is used to enable the SVA bit in Register MAR D6 NSAN No Space Attention Register Notify This bit is used to enable the NSA bit in Register MAR D7 STAN State Attention Register Notify This bit is used to enable the STA bit in Register MAR 93 |
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