DP83266 datasheet(90/152 Pages) NSC

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70 Control Information (Continued)

System Interface Mode Register 0 (SIMR0)

The System Interface Mode Register 0 (SIMR0) is used to program major operating parameters for the System Interface of the

MACSI device This register should be programmed only at power-on or after a software Master Reset

This register is cleared upon reset

Access Rules

Address

Read

Write

100h

Always

SMLB

SMLQ

VIRT

BIGEND

FLOW

MRST

FABCLK

TEST

Bit

Symbol

Description

TEST

Test Mode

Enables test logic in which the transmitted frames counter will cause a service loss after four

frames instead of 255 frames

FABCLK

Fast ABus Clock

For any AB

CLK frequency greater than LBC (125 MHz) this bit must be zero For an

CLK frequency equal to LBC the User may optionally set this bit Setting this bit causes a slight

optimization of the internal MACSI synchronization timing valid only for the case where AB

CLK e LBC e

125 MHz National recommends that all users leave this bit as zero

MRST

Master Reset

When this bit is set the indicate Request and StatusSpace Machines are placed in Stop

Mode and System Interface registers are initialized to the values shown in Table 7-2 This bit is cleared after

the reset is complete

FLOW

Flow Parity

When this bit is set parity checking is enabled at the MAC Indicate Data (Receive Data)

interface The MACSI device uses Odd parity at all interfaces The System Interface reports parity errors in the

STARBPE bit (for receive data from the MAC) or the STARERR (for descriptor fetch parity errors) Data

parity does not get checked at the ABus Interface When this bit is set the parity bit for each ABus data byte

flows with the data byte through the internal FIFO and across the MAC Request (Transmit) interface where it

is checked by the Ring Engine Good parity is always generated on ABus If this bit is reset good parity is

generated at the MAC Request interface For the MAC Indicate Data interface the parity check includes the

frame’s FC through ED fields When this bit is Zero no parity is checked on the MAC Indicate Data interface

In the BSI device this bit also controlled the Control Bus Parity In the MACSI device Control Bus Parity is

enabled using the MCModeCBP bit (see ‘‘MAC Mode Register 0 (MCMR0)’’)

For systems using parity on the ABus the User must initialize the Receive burst FIFO RAM after reset by

doing a send-to-self of a frame at least 64 bytes in length

BIGEND

Big Endian Data Format

Selects between the Little Endian (BIGEND e 0) or Big Endian (BIGEND e 1) data

format See

Figure 6-1

VIRT

Virtual Address Mode

Selects between virtual (VIRT e 1) or physical (VIRT e 0) address mode on the

ABus

SMLQ

Small Queue

Selects the size of all Descriptor queues and lists When SMLQ e 0 the size is 4 kBytes when

SMLQ e 1 the size is 1 kBytes Note that data pages are always 4 kBytes

SMLB

Small Bursts

Selects size of bursts on ABus When SMLB e 0 the MACSI device uses 1- 4- and 8-word

transfers When SMLB e 1 the MACSI device uses 1- and 4-word transfers

DP83266 Datasheet(PDF) 90 Page - National Semiconductor (TI)

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