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DP83266 Datasheet(PDF) 53 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 53 Page - National Semiconductor (TI) |
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53 / 152 page  70 Control Information (Continued) 74 RING ENGINE OPERATION REGISTERS The Operation Registers are used to control the operation of the Ring Engine The Operation Registers include the following registers MAC Mode Register (MCMR0 MCMR2) Option Register (Option) Function Register (Function) MAC Revision Register (MCRev) MAC Mode Register 0 (MCMR0) The Mode Register contains the current mode of the Ring Engine Access Rules Address Read Write 000h Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 DIAG ILB RES RES PIP MRP CBP RUN Bit Symbol Description D7 DIAG Diagnose Mode Enables access to all Ring Engine registers When set interoperability is not guaranteed This bit should only be set when the Ring Engine is not inserted in a ring Design Note In diagnose mode should an internal error occur the Current Receive and Transmit Status Registers are frozen with the error state until the internal state machine error condition is cleared (IELRRSMERR andor IELRTSMERR) D6 ILB Internal Loopback Enables the internal loopback that connects PRP PRC and PRD7 – 0 to PIP PIC and PID7 – 0 respectively When enabled the PHY Indicate Interface is ignored Since the Ring Engine Transmitter and Receiver work as independent processes a ring can be made operational in this mode albeit consisting only of a single MAC With an operational ring many diagnostic tests can be performed to test out MAC level and system level diagnostics including the Beacon Process the Claim Process Ring Engine frame generation token timers event counters transmission options test of event detection capabilities test of addressing modes test of state machine sequencing options etc In addition a large portion of the system interface logic can be tested such as full duplex transmission to self within the limits of the system interface performance constraints status handling and generation etc The same system tests can also be performed at different levels of loopback including through the various paths within a station through the Configuration Switch of the PLAYERa device and through the Clock Recovery Module of the PLAYERa device System level tests can also be performed through the ring during normal operation D5 – D4 RES Reserved D3 PIP PHY Indicate Parity Enables Odd Parity checking on the PHY Indicate Data pins (PID7 – 0) Parity errors are treated as code violations and cause the byte in error to be replaced with Idle symbols When repeating Parity is passed transparently from PIP to PRP Odd Parity is generated for all internally generated fields Odd Parity is always generated on the PHY Request Data pins (PRD7 – 0) D2 MRP MAC Request Parity Enables Odd Parity checking on the MAC Request Data pins (MRD7 – 0) A parity error causes the transmission to be aborted Odd parity is always generated on MIP D1 CBP Control Bus Parity Enables Odd Parity checking on the Control Bus Data pins (CBD7 – 0) during write operations This applies to both the System Interface block and the Ring Engine (MAC) block Parity errors detected while writing to a MAC register (CBA8 e 0) are reported in the CPE bit of the Exception Status Register (ESR 012Ch) Parity errors detected while writing to the System Interface block (CBA8 e 1) are reported in the CPE bit of the State Attention Register (STAR 106h) In either case the write operation is inhibited Parity is always generated on CBD7 – 0 during read accesses D0 RUN RUNStop 0 Stop Mode All state machines return to and remain in their zero state All counters and timers are disabled The Ring Engine transmits Idle symbols 1 Run Mode Enables operation as a MAC entity The Ring Engine (MAC) must be in Run Mode to achieve an operational Ring 53 |
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