DP83266 datasheet(33/152 Pages) NSC

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60 Functional Description (Service Engine) (Continued)

The MACSI device has a mode for controlling the ABus Ad-

dress Strobe (AB

AS) In the default mode AB

AS is

driven active during the address cycle and remains low

throughout the access In the second mode (SIMR1ASM e

1) AB

AS is driven active during the address cycle and

driven inactive during the remainder of the access This al-

lows AB

AS to be used directly as a clock enable to the

address latching device which reduces the number of exter-

nal components

In Enhanced ABus Mode (EAM) the MACSI device has

fixed address timing which is similar to the Physical address

timing described above The SBus MMU does not require

extra cycles for the address translation

The MACSI device interfaces to byte-addressable memory

but always transfers information in words The MACSI de-

vice uses a word width of 32 data bits plus 4 (1 per byte)

parity bits Parity may be ignored

Bus Transfers

The ABus supports single word accesses and 4-word and

8-word bursts Simple reads and writes involve a single ad-

dress and data transfer Burst reads and writes involve a

single address transfer followed by multiple data transfers

Burst sizes are selected dynamically by the MACSI device

The user can disable 8-word bursts by setting MR0SMLB to

a 1 This forces the MACSI device to use 1-word and 4-word

transactions only

The MACSI device provides the full de-multiplexed address

during an access This includes the word address for each

word of a burst (AB

A 42 ) To use the de-multiplexed

addresses (AB

A 42 ) on MACSI revisions A B or C the

Address Timing Mode bit (SIMR1ATM) must be set equal to

one This causes the word address to come out in the same

cycle as the word of data being accessed The word ad-

dresses signals (AB

A 42 ) may be used in the ‘‘look-

ahead’’ mode (SIMR1ATM e 0) if the user does address

de-multiplexing externally by latching AB

A 275 external-

ly during the address cycle For MACSI revisions D or later

(SI revision t 0x00000058) the User may select either Ad-

dress Timing Mode (SIMR1ATM e 0 or 1) while using the

demultiplexed address pins AB

A 270

On Indicate Channels when 8-word bursts are enabled all

transactions will be 8 words until the end of the frame the

last transfer will be 4 or 8 words depending on the number

of remaining bytes If only 4-word bursts are allowed all

Indicate Data transfers are 4 words

On Request Channels the MACSI device will use 4- or

8-word bursts to access all data up to the end of the ODU If

8-word bursts are enabled the first access will be an 8-word

burst if the ODU begins less than 4 words from the start of

an 8-word burst boundary If 8-word bursts are not allowed

or if the ODU begins 4 or more words from the start of an 8-

word burst boundary a 4-word burst will be used The

MACSI device will ignore unused bytes if the ODU does not

start on a burst boundary At the end of an ODU the MACSI

device will use the smallest transfer size (1 4 or 8 words)

which completes the ODU read To coexist in a system that

assumes implicit wrap-around for the addresses within a

burst the MACSI device never emits a burst that will wrap

the 4- or 8-word boundary

A Function Code identifying the type of transaction is output

by the MACSI device on the upper four address bits during

the address phase of a data transfer This can be used for

more elaborate external addressing schemes such as di-

recting control information to one memory and data to an-

other (eg an external FIFO)

Byte Ordering

The basic addressable unit is a byte so request data may be

aligned to any byte boundary in memory All information is

accessed in 32-bit words however so the MACSI device

ignores unused bytes when reading

Descriptors must always be aligned to a 32-bit word address

boundary Input Data Units are always aligned to a burst-

size boundary Output Data Units may be any number of

bytes aligned to any byte-address boundary but operate

most efficiently when aligned to a burst-size boundary Pool

Space Descriptors (PSPs) must point to a burst boundary or

the Receive data will not be written to memory correctly

Burst transfers are always word-aligned on a 16- or 32-byte

(burst-size) address boundary Burst transfers will never

cross a burst-size boundary If a 32-byte transfer size is en-

abled (MR0SMLB e 0) the MACSI device will perform

both 16-byte and 32-byte bursts whichever is most efficient

(least number of clocks to loadstore all required data) If

the MACSI device has less than a full burst of data to com-

plete a frame it will write a full burst Random data is written

to the unused locations The host uses the IDUD length field

to determine where the valid data bytes end

The Bus Interface Unit can operate in either Big Endian or

Little Endian Mode The bit and byte alignments for both

modes are shown in

Figure 6-3 Byte 0 is the first byte re-

ceived from the ring or transmitted to the ring This mode

affects the placement of frame data bytes but it does not

affect the order of Descriptor bytes

Big-Endian Byte Order

D 31

D 0

Word

Halfword 0

Halfword 1

Byte 0

Byte 1

Byte 2

Byte 3

Little-Endian Byte Order

D 31

D 0

Word

Halfword 1

Halfword 0

Byte 3

Byte 2

Byte 1

Byte 0

FIGURE 6-3 ABus Byte Orders

Bus Arbitration

The ABus is a multi-master bus using a simple Bus Re-

questBus Grant protocol that allows an external Bus Arbi-

ter to support any number of bus masters using any arbitra-

tion scheme (eg

rotating or fixed priority) The protocol

provides for multiple transactions per tenure and bus master

preemption

The MACSI device asserts a Bus Request and assumes

mastership when Bus Grant is asserted If the MACSI de-

vice has another transaction pending it will keep Bus Re-

quest asserted or reassert it before the completion of the

DP83266 Datasheet(PDF) 33 Page - National Semiconductor (TI)

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