DP83266 datasheet(99/152 Pages) NSC

99 / 152 page

70 Control Information (Continued)

Bit

Symbol

Description

NSI0

No Status Space on ICHN0

This bit is set by the MACSI device upon a Reset or when an IDUD has been

written to the next-to-last available entry in the Indicate Channel’s IDUD Status Queue When this occurs the

MACSI device stops copying on ICHN0 and the last IDUD is written with special status This bit must be

cleared by the host before the MACSI device will resume copying on this Channel Note that this bit should

only be cleared after the appropriate limit register has been updated to give the MACSI device more status

space

LDI0

Low Data Space on ICHN0

This bit is set by the MACSI device upon Reset or when a PSP is prefetched

from ICHN0’s last PSP Queue location (as defined by the PSP Queue Limit Register) Note that the amount of

warning is dependent on the length of the frame There will always be one more page (4 kBytes) available for

the MACSI device when this attention is generated Another FDDI maximum-length frame (after the current

one) will not fit in this space If PSP fetching was stopped because there were no more PSP entries fetching

will resume automatically when the PSP Queue Limit Register is updated This bit will be cleared automatically

when the new PSP Descriptors are fetched This bit should never be cleared directly by software Clearing this

bit can cause the MACSI device to fetch invalid PSP descriptors

NSR1

No Status Space on RCHN1

This bit is set by the MACSI device upon a Reset or when it has written a CNF

Descriptor to the next-to-last Queue location Due to internal pipelining the MACSI device may write up to two

more CNFs to the Queue after this attention is generated Thus the Host must set the CNF Queue Limit

be cleared by the Host before the MACSI device will continue to process requests on RCHN1 Note that this

bit should only be cleared after the appropriate limit register has been updated to give the MACSI device more

status space

NSR0

No Status Space on RCHN0

This bit is set by the MACSI device upon Reset or when it has been written a

CNF Descriptor to the next-to-last Queue location Due to internal pipelining the MACSI device may write up to

two more CNFs to the Queue after this attention is generated Thus the Host must set the CNF Queue Limit

be cleared by the Host before the MACSI device will continue to process requests on RCHN0 Note that this

bit should only be cleared after the appropriate limit register has been updated to give the MACSI device more

status space

DP83266 Datasheet(PDF) 99 Page - National Semiconductor (TI)