DP83266 datasheet(49/152 Pages) NSC

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70 Control Information (Continued)

TABLE 7-7 MAC Counters and Timer Thresholds

Addr

Name

080 – 086

Reserved

087

THSH1

Null(7 – 4) THSH1(3 – 0)

088 – 092

Reserved

093

TMAX

Null(7 – 4) TMAX(3 – 0)

094 – 096

Reserved

097

TVX

Null(7 – 4) TVX(3 – 0)

098

TNEG0

TNEG(31 – 24)

099

TNEG1

TNEG(23 – 16)

09A

TNEG2

TNEG(15 – 8)

09B

TNEG3

TNEG(7 – 0)

09C – 09E

Reserved

09F

LTCT

LTCT(7 – 0)

0A0

FRCT0

Zero(31 – 24)

0A1

FRCT1

Null(7 – 4) FRCT(19 – 16)

0A2

FRCT2

FRCT(15 – 8)

0A3

FRCT3

FRCT(7 – 0)

0A4

EICT0

Zero(31 – 24)

0A5

EICT1

Null(7 – 4) EICT(19 – 16)

0A6

EICT2

EICT(15 – 8)

0A7

EICT3

EICT(7 – 0)

0A8

LFCT0

Zero(31 – 24)

0A9

LFCT1

Null(7 – 4) LFCT(19 – 16)

0AA

LFCT2

LFCT(15 – 8)

0AB

LFCT3

LFCT(7 – 0)

0AC

FCCT0

Zero(31 – 24)

0AD

FCCT1

Null(7 – 4) FCCT(19 – 16)

0AE

FCCT2

FCCT(15 – 8)

0AF

FCCT3

FCCT(7 – 0)

Addr

Name

0B0

FNCT0

Zero(31 – 24)

0B1

FNCT1

Null(7 – 4) FNCT(19 – 16)

0B2

FNCT2

FNCT(15 – 8)

0B3

FNCT3

FNCT(7 – 0)

0B4

FTCT0

Zero(31 – 24)

0B5

FTCT1

Null(7 – 4) FTCT(19 – 16)

0B6

FTCT2

FTCT(15 – 8)

0B7

FTCT3

FTCT(7 – 0)

0B8

TKCT0

Zero(31 – 24)

0B9

TKCT1

Null(7 – 4) TKCT(19 – 16)

0BA

TKCT2

TKCT(15 – 8)

0BB

TKCT3

TKCT(7 – 0)

0BC

RLCT0

Zero(31 – 24)

0BD

RLCT1

Null(7 – 4) RLCT(19 – 16)

0BE

RLCT2

RLCT(15 – 8)

0BF

RLCT3

RLCT(7 – 0)

Note 1

Null(7–4) indicates that these bits are forced to zero on reads and

are ignored on writes

Note 2

The value obtained on reads from reserved locations is not speci-

fied

Note 3

On Master Reset the event counters are not cleared

The event counters are 20-bit counters and are read

through three control accesses In order to guarantee a

consistent snapshot whenever byte 3 of an event counter is

read byte 1 and byte 2 of the counters are loaded into a

holding register Byte 1 and byte 2 may then be read from

the holding register A single holding register is shared by all

of the counters but (for convenience) is accessible at sever-

al places within the address space Consistent readings

across counters can be accomplished using the Counter

Increment Latch Register (CILR)

The event counters are not reset as a result of a Master

Reset This may be done by either reading the counters out

and keeping track relative to the initial value read or by

writing a value to all of the counters in stop mode The

counters may be written in any order With some excep-

tions interrupts are available when the counters increment

or wraparound

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