DP83266 datasheet(32/152 Pages) NSC

32 / 152 page

60 Functional Description (Service Engine) (Continued)

enabled Therefore for applications which do not use exter-

nal address matching ECIP should be tied low Note also

that if ECIP remains asserted to the point where the incom-

ing frame data completely fills the MACSI device’s Indicate

Data FIFO (4608 bytes for a MACSI device) then the frame

will be dropped due to a FIFO overrun

The LEARN pin provides MAC state machine information

and ring state information useful for building learning bridg-

es The Receive logic of a bridge may wish to avoid copying

frames or learning the source address of frames put on the

ring by this same bridge However use of the Source Ad-

dress Transparency option (SAT) can make recognition of

frames sourced by this bridge difficult The LEARN pin pro-

vides a mechanism for the bridge to determine which

frames and addresses it should copylearn

The MACSI device deasserts the LEARN pin under the fol-

lowing conditions

1 Ring Non-Operational The MACSI device will deassert

the LEARN pin whenever the ring is Non-Operational

2 The Transmitter is holding the Token While this station

holds the Token the only valid frames it should receive

(other than MAC frames which indicate a fault or no-

owner frames that should be ignored in this case) con-

sist of those frames that this station sent Therefore the

MACSI device deasserts the LEARN pin (Actually the

MACSI deasserts LEARN whenever the MAC transmitter

is in the ‘‘Repeat’’ state)

3 For the duration of ‘‘My

Void Stripping’’ The My

Void

Stripping mechanism allows the MACSI device to strip

frames from the ring that it sent using Source Address

Transparency Before releasing the Token the MACSI

device releases two My

Void frames It continues to

strip until the Receiver recognizes at least one My

Void

(or other MAC) frame LEARN will remain low during

Void stripping

4 The Source Address field equals ‘‘My Long Address’’

(MLA) If the internal address matching logic recognizes

the source address of the incoming frame as its own the

MACSI device will deassert the LEARN pin

5 Frames using short (16-bit) address The MACSI deas-

serts the LEARN pin for all frames that use 16-bit ad-

dresses (FCL e 0) Learning bridges usually work with

48-bit addresses

Thus the MACSI device will only assert LEARN for 48-bit

addressed frames that this station did not source (Source

Address i MLA and Not My

Void stripping) received

while the ring is Operational

External logic monitoring the LEARN pin must sample it at

the appropriate point for each received frame Measured at

the MACSIPLAYERa interface (PID) the LEARN pin be-

comes valid at the 4th byte of the Information Field (INFO3)

External logic may sample this pin at INFO3 or later

The MACSI device may or may not assert the LEARN pin at

the beginning of a frame (for the reasons given above) and

LEARN may change state up to INFO3 at the PID interface

Normally LEARN will remain stable during the body of a

frame (up to the End Delimiter) However a MAC Reset a

Master Reset etc may cause the MACSI to deassert the

LEARN pin anywhere within a frame The Designer should

account for these exceptions when designing any logic that

relies on the LEARN pin

The AFLAG Inhibit (AFINHIB available on MACSI revision D

and later) allows the User to suppress the internal Address

matching signal between the MAC and System Interface

The MACSI will ignore the AFINHIB pin until the User sets

the AFLAG Inhibit Enable bit of the MAC Mode Register 2

(MCMR2AFIE) To block an internal address match the

User must assert the AFINHIB input before the 7th byte of

the INFO field as measured at the PID interface

Normally internal matches take precedence over external

matches The User might use AFINHIB to defeat this prece-

dence and steer a frame that matches both an internal and

external address to the external sort channel This pin also

provides an easy mechanism for suppressing the matching

of broadcast (and multicast) frames during bridging For

these applications the User may connect the LEARN pin

directly to the AFINHIB pin This will prevent internal ad-

dress matches of any frame during My

Void stripping

64 BUS INTERFACE UNIT

641 Overview

The ABus provides a 32-bit wide synchronous multiplexed

addressdata bus for transfers between the host system

and the MACSI device The ABus uses a bus requestbus

grant protocol that allows multiple bus masters supports

burst transfers of 16 and 32 bytes and supports virtual and

physical addressing using fixed-size pages The MACSI de-

vice is capable of operating directly on the system bus to

main memory or connected to external shared memory

All bus signals are synchronized to the master bus clock

The maximum burst speed is one 32-bit word per clock but

slower speeds may be accommodated by inserting wait

states The user may use separate clocks for the ring (FDDI

MAC) and system (ABus) interfaces The only restriction is

that the ABus clock must be at least as fast as the ring clock

(LBC) It is important to note that all ABus outputs change

and all ABus inputs are sampled on the rising edge of

CLK

The MACSI device has two major modes of ABus operation

The default or ‘‘normal’’ mode corresponds to the original

BSI device and is completely backward compatible The

second mode is the Enhanced ABus mode This mode is

intended to reduce the logic required to interface to the

SBus originally developed by Sun Microsystems Inc When

the enhanced mode is selected the MACSI device timing

and interface signals are modified slightly to create a closer

fit to the SBus This lowers the cost and eases design of

SBus FDDI adapter cards This new mode is accessible by

programming a mode bit in a register (MR1EAM e 1) This

bit is set to an inactive state upon reset to maintain back-

ward compatibility with the original BSI device

Addressing Modes

In the default ABus mode The Bus Interface Unit has two

Address Modes as selected by the user Physical Address

Mode and Virtual Address Mode In Physical Address Mode

the MACSI device emits the memory address and immedi-

ately begins transferring the data In Virtual Address Mode

the

MACSI

device

inserts

two

clock

cycles

and

TRI-STATE

the address between emitting the virtual ad-

dress and starting to transfer the data This allows virtual-to-

physical address translation by an external memory map-

ping unit (MMU)

DP83266 Datasheet(PDF) 32 Page - National Semiconductor (TI)

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