DP83266 datasheet(6/152 Pages) NSC

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20 General Features (Continued)

In addition to the 46 kByte data FIFOs both the transmit

and receive data paths contain Burst FIFO Blocks each of

which are organized as two banks of eight 32-bit words

221 FRAME-PER-PAGE-PER-CHANNEL

The MACSI device has a feature which allows control of the

Frame-per-Page mode (available on the BSI device) on a

per-Channel basis For example this is useful in systems

where Frame-per-Page mode is used to speed up memory

space reclamation on an LLC channel but where packing

multiple frames into each page is desired to save space on

the SMT channel

222 COPY ALL MULTICAST

The MACSI provides a copy mode which allows all frames

which are addressed with multicast addresses to be copied

Multicast addresses are those that have the Individual

Group address bit (most significant bit of the FDDI address)

set This simple scheme allows flexibility in the use of multi-

cast addresses The MACSI device copies all multicast

frames and software makes the final determination as to

which multicast groups this station belongs

223 BRIDGE STRIPPING INFORMATION

The MACSI device provides an output designed to make it

easier to build transparent bridges Source Address Trans-

parency features are provided as well as features to allow

these frames to be stripped from the ring For transparent

bridges it is important to know when the MACSI is using this

stripping feature to remove frames from the ring which were

forwarded by this bridge but with an unknown source ad-

dress (ie Source Address Transparency enabled) This is

important because the bridge does not want to ‘‘learn’’

these addresses This feature is provided by the MACSI in

the form of an output pin indicating which frames contain

addresses which should be added to the address filter table

(ie learned)

224 LED STATUS CONTROL OUTPUTS

The MACSI device (revision D and later) provides two out-

puts that give Transmit and Receive status information use-

ful for controlling LEDs The MACSI asserts the TXLED pin

each time that it detects that the Request State machine

has entered the ‘‘sending’’ state (once per transmitted

frame) Note that it will not assert TXLED for internally gen-

erated MAC frames It asserts the RXLED pin each time it

detects the End Delimiter of a copied frame (VCOPY and

EDRCVD) Both of these pins use Open Drain output struc-

tures (this preserves pin compatibility with MACSI devices

prior to revision D) Therefore they require pull-up resistors

when used for LED control information To increase the LED

on-time for visibility the User must supply one-shot circuits

triggered by TXLED and RXLED

225 JTAG BOUNDARY SCAN

The MACSI device supports the JTAG boundary scan stan-

dard (IEEE Std 11491 – 1990)

30 Architectural Description

The MACSI is derived from the BMAC and BSI devices The

MACSI is composed of the Ring Engine the Service Engine

and the Bus Interface Unit The Ring Engine performs the

FDDI MAC Timed token protocol and contains the MAC

transmitter and receiver The Service Engine implements

the Request and Indicate Data Services and contains the

Transmit and Receive Data FIFOs The Bus Interface Unit

implements the high speed synchronous bus handshake

and contains the Burst FIFOs

The MACSI device uses a full duplex architecture and pro-

vides sufficient bandwidth at the ABus for full duplex trans-

mission with support for through parity

Figure 3-1 shows

the MACSI device architecture

TLF11705 – 2

FIGURE 3-1 MACSI Device Block Diagram

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