DP83266 datasheet(67/152 Pages) NSC

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70 Control Information (Continued)

Counter Increment Mask Register (CIMR)

The Counter Increment Mask Register (CIMR) is used to mask bits from the Counter Increment Latch Register (CILR) If a bit in

Register CIMR is set to One the corresponding bit in Register CILR will be applied to the Interrupt Condition Register which can

then be used to generate an interrupt to the CPU

All bits in this register are set to Zero upon reset

Access Rules

Address

Read

Write

019h

Always

RES

TKRCVD

FRTRX

FRNCOP

FRCOP

FRLST

FREI

FRRCV

Bit

Symbol

Description

RES

Reserved

TKRCVD

Token Received Counter Increment Mask

This bit is used to mask CILRTKRCVD

FRTRX

Frame Transmitted Counter Increment Mask

This bit is used to mask CILRFRTRX

FRNCOP

Frame Not Copied Counter Increment Mask

This bit is used to mask CILRFRNCOP

FRCOP

Frame Copied Counter Increment Mask

This bit is used to mask CILRFRCOP

FRLST

Lost Frame Counter Increment Mask

This bit is used to mask CILRFRLST

FREI

Error Isolated Counter Increment Mask

This bit is used to mask CILRFREI

FRRCV

Frame Received Counter Increment Mask

This bit is used to mask CILRFRRCV

DP83266 Datasheet(PDF) 67 Page - National Semiconductor (TI)

DP83266 Datasheet(HTML) 67 Page - National Semiconductor (TI)

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