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DP83266 Datasheet(PDF) 59 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 59 Page - National Semiconductor (TI) |
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59 / 152 page  70 Control Information (Continued) Current Receiver Status Register (CRS0) The Current Receiver Status Register (CRS0) records the status of the Receiver state machine It is continuously updated It remains stable when accessed When in Diagnose Mode this register is frozen on an internal error until the internal error event is cleared by resetting the RSMERR bit in the Internal Event Latch Register Access Rules Address Read Write 00Ch Always Data Ignored Register Bits D7 D6 D5 D4 D3 D2 D1 D0 RFLG RS2 RS1 RS0 RES RTS2 RTS1 RTS0 Bit Symbol Description D7 RFLG R Flag Current value of the Restricted Flag When not holding the token indicates the type of the last valid token received When holding the token indicates the type of token that will be issued at the end of the current service opportunity 0 Non-Restricted 1 Restricted D6–D4 RS(2–0) Receive State RS(2 – 0) represent the current state of the Receive state machine that implements the ANSI X3T95 standard MAC Receive Functions The encoding is shown below RS2 RS1 RS0 Receive State 0 0 0 Listen 0 0 1 Await SD 010 RC FR CTRL (Receive FC) 011 RC FR BODY (Receive Frame Body) 100 RC FR STATUS (A and C Indicators ) 1 0 1 CHECK TOKEN (Check Token) 110 RC FR STATUS (Optional Indicators) 1 1 1 Reserved D3 RES Reserved D2 – D0 RTS(2 – 0) Receive Timing State RTS(2 – 0) represent the current state of the Receiver Timing state machine The encoding is shown below RTS2 RTS1 RTS0 Receive Timing State 0 0 0 Await SD 0 0 1 Check FC 0 1 0 Check SA 0 1 1 Check DA 1 0 0 Check INFO 1 0 1 Check MAC 1 1 x Reserved 59 |
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