DP83266 datasheet(96/152 Pages) NSC

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70 Control Information (Continued)

Service Attention Register (SAR)

The Service Attention Register (SAR) is used to present the attentions for the service functions Each bit may be enabled by

setting the corresponding bit in the State Notify Register

This register is set to the value 0Fh upon reset

Access Rules

Address

Read

Write

108h

Always

Conditional

RES

ABR0

ABR1

LMOP

PTOP

Bit

Symbol

Description

PTOP

Pointer RAM Operation

This bit is cleared by the host to cause the MACSI device to transfer data

between a Pointer RAM Register and a predefined mailbox location in memory The Pointer RAM Control

and Address Register contains the Pointer RAM Register address and determines the direction of the

transfer (read or write) The memory address is defined via the Mailbox Address Register This bit is set by

the MACSI device after it performs the data transfer

While PTOP e 0 the host must not alter the Pointer RAM Address and Control Register or the Mailbox

Address Register

LMOP

Limit RAM Operation

This bit is cleared by the host to cause the MACSI device to transfer data between

a Limit RAM Register and the Limit Data and Limit Address Registers The Limit Address Register

contains the Limit RAM Register address and determines the direction of the transfer (read and write)

This bit is set by the MACSI device after it performs the data transfer

While LMOP e 0 the host must not alter either the Limit Address or Limit Data Register

ABR1

Abort Request RCHN1

This bit is cleared by the host to abort a Request on RCHN1 This bit is set by the

MACSI device when RQABORT ends a request on RCHN1 The host may writea1to this bit which may

or may not prevent the request from being aborted When this bit is cleared by the host the USR1 bit in

the Request Attention Register is set and further processing on RCHN1 is halted

ABR0

Abort Request RCHN0

This bit is cleared by the host to abort a Request on RCHN0 This bit is set by the

MACSI device when RQABORT ends a request on RCHN0 The host may writea1to this bit which may

or may not prevent the request from being aborted When this bit is cleared by the host the USR0 bit in

the Request Attention Register is set and further processing on RCHN0 is halted

D7 – D4

RES

Reserved

DP83266 Datasheet(PDF) 96 Page - National Semiconductor (TI)

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