DP83266 datasheet(91/152 Pages) NSC

91 / 152 page

70 Control Information (Continued)

System Interface Mode Register1 (SIMR1)

The System Interface Mode Register 1 (SIMR1) is used to program major operating parameters for the System Interface of the

MACSI device This register should be programmed only at power-on or after a software Master Reset

This register is cleared upon reset Access Rules

Address

Read

Write

101h

Always

A31

A30

A29

A28

ATM

ASM

RES

EAM

Bit

Symbol

Description

EAM

Enhanced ABus Mode

This bit controls the Enhanced ABus Mode (EAM) This enhanced mode is

intended to reduce the amount of logic required to interface to the SBus When this bit is reset the

ABus operates as it does on the original BSI device (normal ABus mode) When this bit is set

the AB

A(3128) bits within this register are sourced on the upper nibble of the addressdata lines

during the address cycle Read Data is strobed the cycle after the assertion of AB

ACK The AB

signal is guaranteed to be deasserted for at least two cycles (see

Figure 6-8 through Figure 6-11 ) The

DEN pin becomes an input and the ErrorAcknowledgment combinations are re-encoded

EAM e 0

EAM e 1

ACK

ERR

ACK

DEN

ERR

Function

Ack(2)

Ack(1)

Ack(0)

Wait Cycle

Word Acknowledgement

Retry

Error

Not Supported

RES

Reserved

ASM

Address Strobe Mode

The ASM bit controls the Address Strobe Mode When this bit is reset the

AS signal operates as it does on the BSI device When this bit is set the MACSI device generates

an AB

AS signal which is designed to drive an address latch control line without additional logic (see

Figure 6-6 and Figure 6-7 )

ATM

Address Timing Mode

The ATM bit controls the Address Timing Mode When this bit is reset the

A(42) lines operate as they do on the BSI These lines provide the demultiplexed address of the

next word to be accessed on the ABus When the ATM bit is set the MACSI device provides the

address of the

current word being accessed on the ABus (see Figure 6-6 and Figure 6-7 ) To use the

demultiplexed address pins AB

A (272) on MACSI revision A through C the User must set the ATM

bit For MACSI revision D and later (SI revision t 0x00000058) the User may use the demultiplexed

address pins AB

A (272) with ATM set or reset

D7–D4

A(3128)

Address(3128)

In normal operation (MR1EAM e 0) the MACSI device encodes channel

information on the upper nibble of the AB

AD bus during the address cycle In Enhanced ABus mode

(MR1EAM e 1) the upper nibble of the address lines are driven with the data pattern which the user

has stored in these four bits AB

A(3128)

DP83266 Datasheet(PDF) 91 Page - National Semiconductor (TI)

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