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DP83266 Datasheet(PDF) 66 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 66 Page - National Semiconductor (TI) |
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66 / 152 page  70 Control Information (Continued) Counter Increment Latch Register (CILR) The Counter Increment Latch Register (CILR) records the occurrence of any increment to the SMT Counters in the Ring Engine Each bit corresponds to a counter and is set when the corresponding counter is incremented Each bit may be masked via the Counter Increment Mask Register (CIMR) Access Rules Address Read Write 018h Always Conditional Register Bits D7 D6 D5 D4 D3 D2 D1 D0 RES TKRCVD FRTRX FRNCOP FRCOP FRLST FREI FRRCV Bit Symbol Description D7 RES Reserved D6 TKRCVD Token Received Is set when the Token Received Counter (TKCT) is incremented indicating that a token has been received D5 FRTRX Frame Transmitted Is set when the Frame Transmitted Counter (FTCT) is incremented indicating a frame has been transmitted D4 FRNCOP Frame Not Copied Is set when the Frame Not Copied Counter (FNCT) is incremented indicating a frame could not be copied D3 FRCOP Frame Copied Is set when the Frame Copied Counter (FCCT) is incremented indicating a frame has been copied D2 FRLST Frame Lost Isolated Is set when the Lost Frame Counter (LFCT) is incremented indicating a format error has been detected in the frame D1 FREI Frame Error Isolated Is set when the Error Isolated Counter (EICT) is incremented indicating an error has been isolated D0 FRRCV Frame Received Is set when the Frame Received Counter (FRCT) is incremented indicating the reception of a frame 66 |
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