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DP83266 Datasheet(PDF) 68 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 68 Page - National Semiconductor (TI) |
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68 / 152 page ![]() 70 Control Information (Continued) Counter Overflow Latch Register (COLR) The Counter Overflow Latch Register (COLR) records carry events from the 20th bit of the SMT Counters in the Ring Engine Each bit in the COLR corresponds to an individual counter Each bit may be masked via the Counter Overflow Mask Register (COMR) Access Rules Address Read Write 01Ch Always Conditional Register Bits D7 D6 D5 D4 D3 D2 D1 D0 RES TKRCVD FRTRX FRNCOP FRCOP FRLST FREI FRRCV Bit Symbol Description D7 RES Reserved D6 TKRCVD Token Received Is set to One when the Token Received Counter (TKCT) overflows D5 FRTRX Frame Transmitted Is set to One when the Frame Transmitted Counter (FTCT) overflows D4 FRNCOP Frame Not Copied Is set to One when the Frame Not Copied Counter (FNCT) overflows D3 FRCOP Frame Copied Is set to One when the Frame Copied Counter (FCCT) overflows D2 FRLST Frame Lost Isolated Is set to One when the Lost Frame Counter (LFCT) overflows D1 FREI Frame Error Isolated Is set to One when the Error Isolated Counter (EICT) overflows D0 FRRCV Frame Received Is set to One when the Frame Received Counter (FRCT) overflows 68 |
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