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MC68HC908AP16CFB Datasheet(PDF) 207 Page - Motorola, Inc |
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MC68HC908AP16CFB Datasheet(HTML) 207 Page - Motorola, Inc |
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207 / 440 page ![]() Timebase Module (TBM) Timebase Register Description MC68HC908AP Family — Rev. 2.5 Data Sheet MOTOROLA 207 12.4 Timebase Register Description The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the rate. TBIF — Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over. 1 = Timebase interrupt pending 0 = Timebase interrupt not pending TBR[2:0] — Timebase Rate Selection These read/write bits are used to select the rate of timebase interrupts as shown in Table 12-1. Address: $0051 Bit 7 654321 Bit 0 Read: TBIF TBR2 TBR1 TBR0 0 TBIE TBON R Write: TACK Reset: 00000000 = Unimplemented R = Reserved Figure 12-2. Timebase Control Register (TBCR) Table 12-1. Timebase Rate Selection for OSCCLK = 32.768 kHz TBR2 TBR1 TBR0 Divider Timebase Interrupt Rate Hz ms 0 0 0 262144 0.125 8000 0 0 1 131072 0.25 4000 0 1 0 65536 0.5 2000 0 1 1 32768 1 1000 10 0 64 512 ~2 10 1 32 1024 ~1 11 0 16 2048 ~0.5 1 1 1 8 4096 ~0.24 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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