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MC68HC908AP16CFB Datasheet(PDF) 208 Page - Motorola, Inc |
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MC68HC908AP16CFB Datasheet(HTML) 208 Page - Motorola, Inc |
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208 / 440 page ![]() Timebase Module (TBM) Data Sheet MC68HC908AP Family — Rev. 2.5 208 MOTOROLA NOTE: Do not change TBR[2:0] bits while the timebase is enabled (TBON = 1). TACK — Timebase ACKnowledge The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic 0 to this bit has no effect. 1 = Clear timebase interrupt flag 0 = No effect TBIE — Timebase Interrupt Enabled This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the TBIE bit. 1 = Timebase interrupt enabled 0 = Timebase interrupt disabled TBON — Timebase Enabled This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption when its function is not necessary. The counter can be initialized by clearing and then setting this bit. Reset clears the TBON bit. 1 = Timebase enabled 0 = Timebase disabled and the counter initialized to 0’s 12.5 Interrupts The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR[2:0]. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. The interrupt vector is defined in Table 2-1 . Vector Addresses. Interrupts must be acknowledged by writing a logic 1 to the TACK bit. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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