MC68HC908AP16CFB datasheet(262/440 Pages) MOTOROLA

262 / 440 page

Infrared Serial Communications

Data Sheet

MC68HC908AP Family — Rev. 2.5

262

MOTOROLA

14.6.3.2 Character Reception

During an SCI reception, the receive shift register shifts characters in

from the RxD pin. The SCI data register (IRSCDR) is the read-only buffer

between the internal data bus and the receive shift register.

After a complete character shifts into the receive shift register, the data

portion of the character transfers to the IRSCDR. The SCI receiver full

bit, SCRF, in IRSCI status register 1 (IRSCS1) becomes set, indicating

that the received byte can be read. If the SCI receive interrupt enable bit,

SCRIE, in IRSCC2 is also set, the SCRF bit generates a receiver CPU

interrupt request.

14.6.3.3 Data Sampling

The receiver samples the RxD pin at the RT clock rate. The RT clock is

an internal signal with a frequency 16 times the baud rate. To adjust for

baud rate mismatch, the RT clock is resynchronized at the following

times (see Figure 14-9):

•

After every start bit

•

After the receiver detects a data bit change from logic 1 to logic 0

(after the majority of data bit samples at RT8, RT9, and RT10

returns a valid logic 1 and the majority of the next RT8, RT9, and

RT10 samples returns a valid logic 0)

Figure 14-9. Receiver Data Sampling

RT CLOCK

RESET

START BIT

QUALIFICATION

START BIT

VERIFICATION

DATA

SAMPLING

SAMPLES

CLOCK

RT CLOCK

STATE

START BIT

LSB

SCI_RxD

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB Datasheet(PDF) 262 Page - Motorola, Inc

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