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MC68HC908AP16CFB Datasheet(PDF) 280 Page - Motorola, Inc |
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MC68HC908AP16CFB Datasheet(HTML) 280 Page - Motorola, Inc |
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280 / 440 page ![]() Infrared Serial Communications Data Sheet MC68HC908AP Family — Rev. 2.5 280 MOTOROLA normal operation, clear the SCTE bit by reading IRSCS1 with SCTE set and then writing to IRSCDR. Reset sets the SCTE bit. 1 = IRSCDR data transferred to transmit shift register 0 = IRSCDR data not transferred to transmit shift register TC — Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in IRSCC2 is also set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF — SCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in IRSCC2 is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading IRSCS1 with SCRF set and then reading the IRSCDR. Reset clears SCRF. 1 = Received data available in IRSCDR 0 = Data not available in IRSCDR IDLE — Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in IRSCC2 is also set. Clear the IDLE bit by reading IRSCS1 with IDLE set and then reading the IRSCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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