MC68HC908AP16CFB datasheet(283/440 Pages) MOTOROLA

283 / 440 page

Infrared Serial Communications Interface Module (IRSCI)

I/O Registers

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

283

14.10.5 IRSCI Status Register 2

IRSCI status register 2 contains flags to signal the following conditions:

•

Break character detected

•

Incoming data

BKF — Break Flag Bit

This clearable, read-only bit is set when the SCI detects a break

character on the RxD pin. In IRSCS1, the FE and SCRF bits are also

set. In 9-bit character transmissions, the R8 bit in IRSCC3 is cleared.

BKF does not generate a CPU interrupt request. Clear BKF by

reading IRSCS2 with BKF set and then reading the IRSCDR. Once

cleared, BKF can become set again only after logic 1s again appear

on the RxD pin followed by another break character. Reset clears the

BKF bit.

1 = Break character detected

0 = No break character detected

RPF — Reception in Progress Flag Bit

This read-only bit is set when the receiver detects a logic 0 during the

RT1 time period of the start bit search. RPF does not generate an

interrupt request. RPF is reset after the receiver detects false start bits

(usually from noise or a baud rate mismatch) or when the receiver

detects an idle character. Polling RPF before disabling the SCI

module or entering stop mode can show whether a reception is in

progress.

1 = Reception in progress

0 = No reception in progress

Address:

$0044

Bit 7

654321

Bit 0

Read:

BKF

RPF

Write:

Reset:

00000000

= Unimplemented

Figure 14-17. IRSCI Status Register 2 (IRSCS2)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB Datasheet(PDF) 283 Page - Motorola, Inc

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