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MC68HC908AP16CFB Datasheet(PDF) 282 Page - Motorola, Inc |
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MC68HC908AP16CFB Datasheet(HTML) 282 Page - Motorola, Inc |
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282 / 440 page  Infrared Serial Communications Data Sheet MC68HC908AP Family — Rev. 2.5 282 MOTOROLA Figure 14-16. Flag Clearing Sequence PE — Receiver Parity Error Bit This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates an SCI error CPU interrupt request if the PEIE bit in IRSCC3 is also set. Clear the PE bit by reading IRSCS1 with PE set and then reading the IRSCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected BYTE 1 NORMAL FLAG CLEARING SEQUENCE READ IRSCS1 SCRF = 1 READ IRSCDR BYTE 1 BYTE 2 BYTE 3 BYTE 4 OR = 0 READ IRSCS1 SCRF = 1 OR = 0 READ IRSCDR BYTE 2 READ IRSCS1 SCRF = 1 OR = 0 READ IRSCDR BYTE 3 BYTE 1 READ IRSCS1 SCRF = 1 READ IRSCDR BYTE 1 BYTE 2 BYTE 3 BYTE 4 OR = 0 READ IRSCS1 SCRF = 1 OR = 1 READ IRSCDR BYTE 3 DELAYED FLAG CLEARING SEQUENCE Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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