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ATTINY817-MFR. Datasheet(PDF) 136 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 136 Page - Microchip Technology |
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136 / 492 page  19.2.3.3 Interrupts Not applicable. 19.2.3.4 Events Not applicable. 19.2.3.5 Debug Operation When run-time debugging, this peripheral will continue normal operation. Halting the CPU in debugging mode will halt normal operation of the peripheral. When halting the CPU in debug mode, the WDT counter is reset. when starting the CPU again and the WDT was operating in window mode, the first closed window timeout period will be disabled, and a normal mode timeout period is executed. Related Links Window Mode 19.3 Functional Description 19.3.1 Initialization • The WDT is enabled when a non-zero value is written to the Period bits (PERIOD) in the Control A register (WDT.CTRLA). • Optional: Write a non-zero value to the Window bits (WINDOW) in WDT.CTRLA to enable window mode operation. All bits in the Control A register and the Lock bit (LOCK) in the Status register (WDT.STATUS) are write protected by the Configuration Change Protection mechanism. The Reset value of WDT.CTRLA is defined by a fuse (FUSE.WDTCFG), so the WDT can be enabled at boot time. If this is the case, the LOCK bit in WDT.STATUS is set at boot time. Related Links Register Summary - WDT 19.3.2 Operation 19.3.2.1 Normal Mode In normal mode operation, a single timeout period is set for the WDT. If the WDT is not reset from software using the WDR any time before the timeout occurs, the WDT will issue a System Reset. A new WDT timeout period will be started each time the WDT is reset by WDR. There are 11 possible WDT timeout periods (TOWDT), selectable from 8ms to 8s by writing to the Period bit field (PERIOD) in the Control A register (WDT.CTRLA). ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 136 |
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