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ATTINY817-MFR. Datasheet(PDF) 137 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 137 Page - Microchip Technology |
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137 / 492 page ![]() Figure 19-2. Normal Mode Operation t [ms] WDT Count 5 10 15 20 25 30 35 Timely WDT Reset (WDR) TOWDT WDT Timeout System Reset TO WDT = 16ms Here: Normal mode is enabled as long as the WINDOW bit field in the Control A register (WDT.CTRLA) is 0x0. Related Links Register Summary - WDT 19.3.2.2 Window Mode In window mode operation, the WDT uses two different timeout periods, a "closed" window timeout period (TOWDTW) and the normal timeout period (TOWDT): The closed window timeout period defines a duration from 8ms to 8s where the WDT cannot be reset. If the WDT is reset during this period, the WDT will issue a System Reset. The normal WDT timeout period, which is also 8ms to 8s, defines the duration of the "open" period during which the WDT can (and should) be reset. The open period will always follow the closed period, so the total duration of the timeout period is the sum of the closed window and the open window timeout periods. When enabling window mode or when going out of debug mode, the first closed period is activated after the first WDR instruction. If a second WDR is issued while a previous WDR is being synchronized, the second one will be ignored. Figure 19-3. Window Mode Operation t [ms] WDT Count 5 10 15 20 25 30 35 Timely WDT Reset (WDR) TOWDTW TOWDT System Reset WDR too early: TOWDTW =TOWDT = 8ms Here: The window mode is enabled by writing a non-zero value to the WINDOW bit field in the Control A register (WDT.CTRLA), and disabled by writing WINDOW=0x0. 19.3.2.3 Configuration Protection and Lock The WDT provides two security mechanisms to avoid unintentional changes to the WDT settings: ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 137 |
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