ATTINY817-MFR. datasheet(141/492 Pages) MICROCHIP

141 / 492 page

The bits are optionally lock protected:

•

If LOCK in WDT.STATUS is '1', all bits are change protected (Access = R)

•

If LOCK in WDT.STATUS is '0', all bits can be changed (Access = R/W)

Value

Name

Description

0x0

OFF

0x1

8CLK

0.008s

0x2

16CLK

0.016s

0x3

32CLK

0.032s

0x4

64CLK

0.064s

0x5

128CLK

0.128s

0x6

256CLK

0.256s

0x7

512CLK

0.512s

0x8

1KCLK

1.0s

0x9

2KCLK

2.0s

0xA

4KCLK

4.1s

0xB

8KCLK

8.2s

other

Reserved

19.5.2

Status

Name:

STATUS

Offset: 0x01

Reset:

0x00

Property:

Configuration Change Protection

Bit

LOCK

SYNCBUSY

Access

R/W

Reset

Bit 7 – LOCK: Lock

Writing this bit to '1' write protects the WDT.CTRLA register.

It is only possible to write this bit to '1'. This bit can only be cleared in debug.

If the PERIOD bits in WDT.CTRLA are different from zero after boot code, Lock will automatically be set.

This bit is under Configuration Change Protection (CCP).

Bit 0 – SYNCBUSY: Synchronization Busy

This bit is set after writing to the WDT.CTRLA register while the data is being synchronized from the

system clock domain to the WDT clock domain.

This bit is cleared by system after the synchronization is finished.

This bit is not under Configuration Change Protection (CCP).

ATTINY817-MFR. Datasheet(PDF) 141 Page - Microchip Technology

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