ATTINY817-MFR. datasheet(138/492 Pages) MICROCHIP

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The first mechanism is the Configuration Change Protection mechanism, employing a timed write

procedure for changing the WDT control registers.

The second mechanism locks the configuration by writing a '1' to the LOCK bit in the Status register

(WDT.STATUS). When this bit is '1', the Control A register (WDT.CTRLA) cannot be changed.

Consequently, the WDT cannot be disabled from software.

LOCK in WDT.STATUS can only be written to '1'. It can only be cleared in debug mode.

If the WDT configuration is loaded from fuses, LOCK is automatically set in WDT.STATUS.

Related Links

CCP - Configuration Change Protection

19.3.3

Events

Not applicable.

19.3.4

Interrupts

Not applicable.

19.3.5

Sleep Mode Operation

The WDT will continue to operate in any sleep mode where the source clock is active.

19.3.6

Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domain, the Control A

Status register (WDT.STATUS) indicates if there is an ongoing synchronization.

Writing to WDT.CTRLA while SYNCBUSY=1 is not allowed.

The following registers are synchronized when written:

•

PERIOD bits in Control A register (WDT.CTRLA)

•

Window Period bits (WINDOW) in WDT.CTRLA.

The WDR instruction will need 2 to 3 cycles of the WDT clock in order to be synchronized. Issuing a new

WDR instruction while a WDR instruction is being synchronized will be ignored

19.3.7

Configuration Change Protection

This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to

these, a certain key must be written to the CPU.CCP register first, followed by a write access to the

protected bits within four CPU instructions.

It is possible to try writing to these registers any time, but the values are not altered.

The following registers are under CCP:

Table 19-2. WDT - Registers under Configuration Change Protection

Key

WDT.CTRLA

IOREG

LOCK bit in WDT.STATUS

IOREG

List of bits/registers protected by CCP.

•

Period bits in Control A register (CTRLA.PERIOD)

ATtiny417/817

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