ATTINY817-MFR. datasheet(164/492 Pages) MICROCHIP

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20.5.11 Interrupt Flag Register - Normal Mode

The individual status bit can be cleared by writing a '1'e to its bit location. This allows each bit to be set

without use of a read-modify-write operation on a single register.

Name:

INTFLAGS

Offset: 0x0B

Reset:

0x00

Property:

Bit

CMP2

CMP1

CMP0

OVF

Access

R/W

Reset

Bit 6 – CMP2: Compare Channel 2 Interrupt Flag

See CMP0 flag description.

Bit 5 – CMP1: Compare Channel 1 Interrupt Flag

See CMP0 flag description.

Bit 4 – CMP0: Compare Channel 0 Interrupt Flag

The compare interrupt flag (CMPn) is set on a compare match on the corresponding compare channel.

For all modes of operation, the CMPn flag will be set when a compare match occurs between the count

automatically and has to be cleared by software. This is done by writing a one to its bit location.

Bit 0 – OVF: Overflow/Underflow Interrupt Flag

This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the

WGMODE setting. OVF is not automatically cleared and needs to be cleared by software. This is done by

writing a one to its bit location.

20.5.12 Debug Control Register

Name:

DBGCTRL

Offset: 0x0E

Reset:

0x00

Property:

Bit

DBGRUN

Access

R/W

Reset

Bit 0 – DBGRUN: Run in Debug

Value

Description

The peripheral is halted in break debug mode and ignores events.

The peripheral will continue to run in break debug mode when the CPU is halted.

ATtiny417/817

Datasheet Complete

DS40001901B-page 164

ATTINY817-MFR. Datasheet(PDF) 164 Page - Microchip Technology

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