ATTINY817-MFR. datasheet(161/492 Pages) MICROCHIP

161 / 492 page

Name:

CTRLESET

Offset: 0x05

Reset:

0x00

Property:

Bit

CMD[1:0]

LUPD

DIR

Access

R/W

Reset

Bits 3:2 – CMD[1:0]: Command

These bits are used for software control of update, restart, and reset of the timer/counter. The command

bits are always read as zero.

Value

Name

Description

0x0

NONE

No command

0x1

UPDATE

Force update

0x2

RESTART

Force restart

0x3

RESET

Force hard Reset (ignored if TC is enabled)

Bit 1 – LUPD: Lock Update

Locking the update ensures that all buffers are valid before an update is performed.

Value

Description

The buffered registers are updated as soon as an UPDATE condition has occurred.

No update of the buffered registers is performed, even though an UPDATE condition has

occurred.

Bit 0 – DIR: Counter Direction

Normally this bit is controlled in hardware by the waveform generation mode or by event actions, but this

bit can also be changed from software.

Value

Description

The counter is counting up (incrementing).

The counter is counting down (decrementing).

20.5.7

Control Register F Clear

The individual status bit can be cleared by writing a one to its bit location. This allows each bit to be

cleared without use of a read-modify-write operation on a single register.

Name:

CTRLFCLR

Offset: 0x06

Reset:

0x00

Property:

ATtiny417/817

Datasheet Complete

DS40001901B-page 161

ATTINY817-MFR. Datasheet(PDF) 161 Page - Microchip Technology

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