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ATTINY817-MFR. Datasheet(PDF) 159 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 159 Page - Microchip Technology |
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159 / 492 page ![]() Value Name Description 0x0 NORMAL Normal operation mode 0x1 FRQ Frequency mode 0x3 SINGLESLOPE Single-slope PWM mode 0x5 DSTOP Dual-slope PWM mode 0x6 DSBOTH Dual-slope PWM mode 0x7 DSBOTTOM Dual-slope PWM mode Other - Reserved 20.5.3 Control C - Normal Mode Name: CTRLC Offset: 0x02 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 CMP2OV CMP1OV CMP0OV Access R/W R/W R/W Reset 0 0 0 Bit 2 – CMP2OV: Compare Output Value 2 See CMP0OV. Bit 1 – CMP1OV: Compare Output Value 1 See CMP0OV. Bit 0 – CMP0OV: Compare Output Value 0 The CMPnOV bits allow direct access to the waveform generator's output compare value when the timer/ counter is not enabled. This is used to set or clear the WG output value when the timer/counter is not running. 20.5.4 Control D Name: CTRLD Offset: 0x03 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SPLITM Access R/W Reset 0 Bit 0 – SPLITM: Enable Split Mode This bit sets the timer/counter in split mode operation. It will then work as two 8-bit timer/counters. The register map will change compared to normal 16-bit mode. ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 159 |
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