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ATTINY817-MFR. Datasheet(PDF) 157 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 157 Page - Microchip Technology |
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157 / 492 page ![]() 20.5 Register Description - Normal Mode 20.5.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 CLKSEL[2:0] ENABLE Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 3:1 – CLKSEL[2:0]: Clock Select These bits select the clock frequency for the timer/counter. Value Name Description 0x0 DIV1 fTCA = fCLK_PER/1 0x1 DIV2 fTCA = fCLK_PER/2 0x2 DIV4 fTCA = fCLK_PER/4 0x3 DIV8 fTCA = fCLK_PER/8 0x4 DIV16 fTCA = fCLK_PER/16 0x5 DIV64 fTCA = fCLK_PER/64 0x6 DIV256 fTCA = fCLK_PER/256 0x7 DIV1024 fTCA = fCLK_PER/1024 Bit 0 – ENABLE: Enable Value Description 0 The peripheral is disabled 1 The peripheral is enabled 20.5.2 Control B - Normal Mode Name: CTRLB Offset: 0x01 Reset: 0x00 Property: - ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 157 |
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