ATTINY817-MFR. datasheet(172/492 Pages) MICROCHIP

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Bit

SPLITM

Access

R/W

Reset

Bit 0 – SPLITM: Enable Split Mode

This bit sets the timer/counter in split mode operation. It will then work as two 8-bit timer/counters. The

20.7.5

Control Register E Clear - Split Mode

The individual status bit can be cleared by writing a '1' to its bit location. This allows each bit to be cleared

without use of a read-modify-write operation on a single register.

Each Status bit can be read out either by reading TCA.CTRLESET or TCA.CTRLECLR.

Name:

CTRLECLR

Offset: 0x04

Reset:

0x00

Property:

Bit

CMD[1:0]

Access

R/W

Reset

Bits 3:2 – CMD[1:0]: Command

These bits are used for software control of update, restart, and reset of the timer/counter. The command

bits are always read as zero.

Value

Name

Description

0x0

NONE

No command

0x1

UPDATE

Force update

0x2

RESTART

Force restart

0x3

RESET

Force hard Reset (ignored if TC is enabled)

20.7.6

Control Register E Set - Split Mode

The individual status bit can be set by writing a '1' to its bit location. This allows each bit to be set without

use of a read-modify-write operation on a single register.

Each Status bit can be read out either by reading TCA.CTRLESET or TCA.CTRLECLR.

Name:

CTRLESET

Offset: 0x05

Reset:

0x00

Property:

ATtiny417/817

Datasheet Complete

DS40001901B-page 172

ATTINY817-MFR. Datasheet(PDF) 172 Page - Microchip Technology

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