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ATTINY817-MFR. Datasheet(PDF) 175 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 175 Page - Microchip Technology |
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175 / 492 page ![]() 20.7.10 Low-byte Timer Counter Register - Split Mode TCA.LCNT contains the counter value in low-byte timer. CPU and UPDI write access has priority over count, clear, or reload of the counter. Name: LCNT Offset: 0x20 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 LCNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – LCNT[7:0]: Counter value for low-byte timer These bits define the counter value of the low-byte timer. 20.7.11 High-byte Timer Counter Register - Split Mode TCA.HCNT contains the counter value in high-byte timer. CPU and UPDI write access has priority over count, clear, or reload of the counter. Name: HCNT Offset: 0x21 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 HCNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – HCNT[7:0]: Counter value for high-byte timer These bits define the counter value in high-byte timer. 20.7.12 Low-byte Timer Period Register - Split Mode The TCA.LPER register contains the TOP value of low-byte timer. Name: LPER Offset: 0x26 Reset: 0x00 Property: - ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 175 |
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