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ATTINY817-MFR. Datasheet(PDF) 174 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 174 Page - Microchip Technology |
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174 / 492 page ![]() Name: INTFLAGS Offset: 0x0B Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 LCMP2 LCMP1 LCMP0 HUNF LUNF Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 6 – LCMP2: Low-byte Compare Channel 0 Interrupt Flag See LCMP0 flag description. Bit 5 – LCMP1: Low-byte Compare Channel 0 Interrupt Flag See LCMP0 flag description. Bit 4 – LCMP0: Low-byte Compare Channel 0 Interrupt Flag The compare interrupt flag (LCMPn) is set on a compare match on the corresponding compare channel. For all modes of operation, the LCMPn flag will be set when a compare match occurs between the Low- byte count register (LCNT) and the corresponding compare register (LCMPn). The LCMPn flag will not be cleared automatically and has to be cleared by software. This is done by writing a ‘1’ to its bit location. Bit 1 – HUNF: High-byte Underflow Interrupt Flag This flag is set on a high-byte timer BOTTOM (underflow) condition. HUNF is not automatically cleared and needs to be cleared by software. This is done by writing a ‘1’ to its bit location. Bit 0 – LUNF: Low-byte Underflow Interrupt Flag This flag is set on a low-byte timer BOTTOM (underflow) condition. LUNF is not automatically cleared and needs to be cleared by software. This is done by writing a ‘1’ to its bit location. 20.7.9 Debug Control Register Name: DBGCTRL Offset: 0x0E Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN: Run in Debug Value Description 0 The peripheral is halted in break debug mode and ignores events. 1 The peripheral will continue to run in break debug mode when the CPU is halted. ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 174 |
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