MCP37D11-80ESLASHTE datasheet(32/136 Pages) MICROCHIP

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MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

DS20006381A-page 32

 2020 Microchip Technology Inc.

4.2

Supply Voltage (DVDD, AVDD, GND)

The device operates from two sets of supplies and a

common ground:

• Digital Supplies (DVDD) for the digital section:

1.8V and 1.2V

• Analog Supplies (AVDD) for the analog section:

1.8V and 1.2V

• Ground (GND): Common ground for both digital

and analog sections.

The supply pins require an appropriate bypass

capacitor (ceramic) to attenuate the high-frequency

noise present in most application environments. The

ground pins provide the current return path. These

ground pins must be connected to the ground plane of

the PCB through a low-impedance connection. A

ferrite bead can be used to separate analog and digital

supply lines if a common power supply is used for both

analog and digital sections.

The voltage regulators for each supply need to have

sufficient output current capabilities to support a stable

ADC operation.

4.2.1

POWER-UP SEQUENCE

Figure 2-5 shows the internal power-up sequence

events of the device. The power-up sequence of the

device is initiated by a Power-on reset (POR) circuit

which monitors the analog 1.2V supply voltage

(AVDD12):

(a) Once the AVDD12 reaches the Power-on Reset

threshold (~ 0.8V), there will be a Power-on Reset

stabilization period (218 clock cycles) before triggering

the power-up calibration (TPCAL).

(b) All other supply voltages (AVDD18, DVDD18,

DVDD12) must be stabilized before or within the POR

stabilization period (TPOR-S). The order that these

supply voltages are applied and stabilized will not affect

the power-up sequence.

4.3

Input Sample Rate

In single-channel mode, the device samples the input

at full speed. In multi-channel mode, the core ADC is

multiplexed between the selected channels. The

resulting effective sample rate per channel is shown in

Equation 4-1.

For example, with 80 Msps operation, the input is

sampled at the full 80 Msps rate if a single channel is

used, or at 10 Msps per channel if all eight channels

are used.

EQUATION 4-1:

SAMPLE RATE PER

CHANNEL

4.4

Analog Input Channel Selection

The analog input is auto-multiplexed sequentially as

defined by the channel-order selection bit setting. The

user can configure the input MUX using the following

registers:

• SEL_NCH<2:0> in Address 0x01 (Register 5-2):

Select the total number of input channels to be

used.

• Addresses 0x7D – 0x7F (Registers 5-38–5-40):

Select auto-scan channel order.

The user can select up to eight input channels. If all

eight input channels are to be used, SEL_NCH<2:0> is

set to 000 and the input channel sampling order is set

using Addresses 0x7D – 0x7F (Registers 5-38–5-40).

Regardless of how many channels are selected, all

eight channels must be programmed in Addresses

0x7D – 0x7F (Registers 5-38–5-40) without duplica-

tion. Program the addresses of the selected channels

in sequential order, followed by the unused channels.

The order of the unused channels has no effect. The

device samples the first N-Channels listed in

Addresses

0x7D – 0x7F

(Registers 5-38–5-40)

sequentially, where N is the total number of channels to

be used, defined by the SEL_NCH<2:0>. Table 4-1

shows examples of input channel selection using

Addresses 0x7D – 0x7F (Registers 5-38–5-40).

Sample Rate/Channel

Full ADC Sample Rate fs



Number of Channel Used

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