MCP37D11-80ESLASHTE datasheet(41/136 Pages) MICROCHIP

41 / 136 page

 2020 Microchip Technology Inc.

DS20006381A-page 41

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

FIGURE 4-11:

Timing Clock Control Blocks.

VCO

Phase/Freq.

Detector

(3rd Order)

Output/Div

PLL_PRE<11:0>

PLL_REFDIV<9:0>

Current

PLL_OUTDIV<3:0>

PLL Block

Input Clock Buffer

EN_DUTY

C1: PLL_CAP1<4:0>

PLL_CHAGPUMP<3:0>

Loop Filter Control

C2: PLL_CAP2<4:0>

C3: PLL_CAP3<4:0>

R1: PLL_RES<4:0>

Loop Filter

(80 MHz - 250 MHz)

PLL Output Control Block

Pump

Loop Filter Control Parameters:

fVCO

See Address 0x54 - 0x5D for Control Parameters

See Address 0x55 and 0x6D

÷N

÷R

if CLK_SOURCE = 1

Charge

Clock Input (fCLK): < 250 MHz

fREF

Duty Cycle Correction (DCC)

EN_DLL

Phase Delay

DCLK_PHDLY_DLL<2:0>

DCLK

EN_CLK

DLL Block

EN_PLL_CLK

DCLK Delay

DCLK_DLY_PLL<2:0>

for control parameters

if CLK_SOURCE = 0

Note:

VCO output range is 1.075 GHz – 1.325 GHz by setting PLL_REFDIV<10:0> and PLL_PRE<11:0>, with fREF = 5 MHz - 250 MHz range.

fVCO

----fREF



1.075 1.325

–

 GHz

EN_PLL_REFDIV

Digital Output

Clock Phase Delay Control

Clock Rate Control

Digital Output

Digital Clock Output Control Block

DCLK

if digital decimation is used

OUT_CLKRATE<3:0>

RESET_DLL

EN_DLL_DCLK

DCLK_PHDLY_DEC<2:0>

EN_PHDLY

DCLK

See Address 0x64 and 0x02

for control parameters

See Address 0x52 and 0x64<7> for details

if digital decimation is used

See Address 0x7A, 0x7B, 0x7C, and 0x81

(5 MHz to 250 MHz)

(when decimation filter is used)

EN_PLL

EN_PLL_BIAS

EN_PLL_OUT

EN_DLL = 0

EN_DLL_DCLK = 0

See Address 0x7A, 0x7B, 0x7C, and 0x81

EN_PHDLY

DLL Circuit

DCLK

MCP37D11-80E/TE Datasheet(PDF) 41 Page - Microchip Technology

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