MCP37D11-80ESLASHTE datasheet(83/136 Pages) MICROCHIP

83 / 136 page

 2020 Microchip Technology Inc.

DS20006381A-page 83

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

ADDRESS 0X55 – PLL OUTPUT AND REFERENCE DIVIDER

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

PLL_OUTDIV<3:0>

FCB<1:0>

PLL_REFDIV<9:8>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

PLL_OUTDIV<3:0>: PLL output divider control bits(1)

1111 = PLL output divided by 15

1110 = PLL output divided by 14

• • •

0100 = PLL output divided by 4 (Default)

0011 = PLL output divided by 3

0010 = PLL output divided by 2

0001 = PLL output divided by 1

0000 = PLL output not divided

bit 3-2

FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.

bit 1-0

PLL_REFDIV<9:8>: Upper two MSb bits of PLL_REFDIV<9:0>(2)

00 = see Table 5-4. (Default)

Note

PLL_OUTDIV<3:0> controls the PLL output clock divider: VCO output is divided by the PLL_OUTDIV<3:0> setting.

See Address 0x54 (Register 5-9) and Table 5-4 for PLL_REFDIV<9:0> settings. EN_PLL_REFDIV in Address 0x59

(Register 5-14) must be set.

TABLE 5-4:

EXAMPLE – PLL REFERENCE DIVIDER BIT SETTINGS VS. PLL REFERENCE INPUT

FREQUENCY

PLL_REFDIV<9:0>

PLL Reference Frequency

11-1111-1111

Reference frequency divided by 1023

11-1111-1110

Reference frequency divided by 1022

──

00-0000-0011

Reference frequency divided by 3

00-0000-0010

Do not use (not supported)

00-0000-0001

Reference frequency divided by 1

00-0000-0000

Reference frequency divided by 1

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