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MCP37D11-80E/TE Datasheet(PDF) 57 Page - Microchip Technology |
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MCP37D11-80E/TE Datasheet(HTML) 57 Page - Microchip Technology |
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57 / 136 page  2020 Microchip Technology Inc. DS20006381A-page 57 MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC TABLE 4-18: OUTPUT TYPE VS. CONTROL PARAMETERS FOR SINGLE-CHANNEL DDC (EXAMPLE) Output Type Control Parameter Register Descriptions Complex: I and Q EN_DDC1 = 1 0X80 Enable DDC1 block EN_NCO = 1 0X80 Enable 32-bit NCO HBFILTER_A = 1 0X80 Enable Half-Band Filter A, includes 2x decimation EN_DDC_FS/8 = 0 0X80 NCO(fS/8/DER) is disabled EN_DDC2 = 0 0X81 DDC2 is disabled FIR_A<8:1>=0x00 0X7B FIR A decimation filter is disabled FIR_B<7:0>=0x00 0X7C FIR B decimation filter is disabled OUT_CLKRATE<3:0> 0X02 Output clock rate is not affected (no need to change) Decimated I and Q:IDEC, QDEC EN_DDC1 = 1 0X80 Enable DDC1 block EN_NCO = 1 0X80 Enable 32-bit NCO HBFILTER_A = 1 0X80 Enable Half-Band Filter A, includes 2x decimation EN_DDC_FS/8 = 0 0X80 NCO(fS/8/DER) is disabled EN_DDC2 = 0 0X81 DDC2 is disabled FIR_A<8:1> 0X7B Program FIR A filter for extra decimation(1) FIR_B<7:0> 0X7C Program FIR B filter for extra decimation(1) OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the decimation rate Real: RealA after DDC(fS/8/DER) without using Decimation Filter EN_DDC1 = 1 0X80 Enable DDC1 block EN_NCO = 1 0X80 Enable 32-bit NCO HBFILTER_A = 1 0X80 Enable Half-Band Filter A, includes 2x decimation EN_DDC_FS/8 = 1 0X80 NCO(fS/8/DER) is enabled. This translates the input signal from dc to fS/8(2) EN_DDC2 = 1 0X81 DDC2 is enabled FIR_A<8:1>=0x00 0X7B Decimation filter FIR A is disabled FIR_B<7:0>=0x00 0X7C Decimation filter FIR B is disabled OUT_CLKRATE<3:0> = 0001 0X02 Adjust the output clock rate to divided by 2(3) Decimated Real: RealA_DEC after Decimation Filter and DDC(fS/8/DER) EN_DDC1 = 1 0X80 Enable DDC1 block EN_NCO = 1 0X80 Enable 32-bit NCO HBFILTER_A = 1 0X80 Enable Half-Band Filter A, includes 2x decimation EN_DDC_FS/8 = 1 0X80 NCO(fS/8/DER) is enabled. This translates the input signal from dc to fS/8/DER(2) EN_DDC2 = 1 0X81 DDC2 is enabled FIR_A<8:1> 0X7B Program FIR B filter for extra decimation(4) FIR_B<7:0> 0X7C Program FIR B filter for extra decimation(4) OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the total decimation rate including the 2x decimation by the Half-Band Filter A Note 1: For I/Q decimation, the maximum decimation rate for the FIR A and FIR B filters is 128x each since the input is already decimated by 2x in the Half-Band Filter. See Figure 4-16 for details. 2: DER is the decimation rate setting of the FIR A and FIR B filters. 3: Divided by 2 is due to the 2x decimation included in the Half-Band Filter A. 4: When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER). |
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