MCP37D11-80ESLASHTE datasheet(9/136 Pages) MICROCHIP

9 / 136 page

 2020 Microchip Technology Inc.

DS20006381A-page 9

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

Notes:

When the VCM output is used for the Common-mode voltage of analog inputs (i.e. by connecting to the center-tap of

a balun), the VCM pin should be decoupled with a 0.1 µF capacitor, and should be directly tied to the VCMIN+ and VCMIN-

pins.

CMOS output mode: WCK/OVR- is WCK and WCK/OVR+ is OVR.

DDR LVDS output mode: The rising edge of DCLK+ is WCK and the falling edge is OVR.

OVR: OVR will be held “High” when analog input overrange is detected. Digital signal post-processing will cause

OVR to assert early relative to the output data. See Figure 2-2 for LVDS timing of these bits.

WCK: WCK is normally “Low”. WCK is “High” while data from the first channel is sent out. In single-channel

mode, WCK stays “High” except when in I/Q output mode. See Section 4.12.4 “Word Clock (WCK)” for further

WCK description.

DDR LVDS: Two data bits are multiplexed onto each differential output pair. The output pins shown here are for

the “Even bit first”, which is the default setting of OUTPUT_MODE<1:0> in Address 0x62 (Register 5-20). The

even data bits (Q0, Q2, Q4, Q6, Q8, Q10) appear when DCLK+ is “High”. The odd data bits (Q1, Q3, Q5, Q7,

Q9, Q11) appear when DCLK+ is “Low”. See Addresses 0x65 (Register 5-23) and 0x68 (Register 5-26) for output

polarity control. See Figure 2-2 for LVDS output timing diagram.

VCMIN is used for Auto-Calibration only. VCMIN+ and VCMIN- should be tied together always. There should be no

voltage difference between the two pins. Typically both VCMIN+ and VCMIN- are tied to the VCM output pin

together, but they can be tied to another Common-mode voltage if external VCM is used. This pin has High Z input

in Shutdown, Standby and Reset modes.

CAL pin stays “Low” at power-up until the first power-up calibration is completed. When the first calibration has

completed, this pin has “High” output. It stays “High” until the internal calibration is restarted by hardware or a

soft reset command. In Reset mode, this pin is “Low”. In Standby and Shutdown modes, this pin will maintain the

prior condition.

If the SPI address is dynamically controlled, the Address pin must be held constant while CS is “Low”.

The phase of DCLK relative to the data output bits may be adjusted depending on the operating mode. This is

controlled differently depending on the configuration of the digital signal post-processing, PLL and/or DLL. Also

see Addresses 0x52, 0x64 and 0x6D (Registers 5-7, 5-22 and 5-28) for more details.

Do not tie to ground or supply.

The device is in Reset mode while this pin stays “Low”. On the rising edge of RESET, the device exits Reset

mode, initializes all internal user registers to default values, and begins power-up calibration.

10. a) SLAVE = “High”: The device is selected as slave and the SYNC pin becomes input pin.

(b) SLAVE = “Low”: The device is selected as master and the SYNC pin becomes output pin. In SLAVE/SYNC

operation, master and slave devices are synchronized to the same clock.

K10

GND

Supply

Common ground for analog and digital sections

K11

Digital

Output

Output test pints. Leave these pins floating always(8)

DCLK-

LVDS: Differential digital clock output (+)

CMOS: Digital clock output(7)

RESET

Digital Input Reset control input:

High: Normal operating mode

Low: Reset mode(9)

SYNC

Digital Input/

Output

Digital synchronization pin for AutoSync.(10)

If not used, leave it floating.

GND

Supply

Common ground for analog and digital sections

CLK+

Analog Input Differential clock input (+)

CLK-

Differential clock input (-)

L10

GND

Supply

Common ground for analog and digital sections

L11

AVDD18

Analog Input Supply voltage input (1.8V) for analog section

TABLE 1-1:

PIN FUNCTION TABLE FOR TFBGA-121 PACKAGE (CONTINUED)

Ball No.

Name

I/O Type

Description

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