MCP37D11-80ESLASHTE datasheet(79/136 Pages) MICROCHIP

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DS20006381A-page 79

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

ADDRESS 0X02 – OUTPUT DATA AND CLOCK RATE CONTROL(1)

R/W-0

OUT_DATARATE<3:0>

OUT_CLKRATE<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

OUT_DATARATE<3:0>: Output data rate control bits

1111 = Output data is all 0’s

1110 = Output data is all 0’s

1101 = Output data is all 0’s

1100 = Internal test only(2)

1011 = Internal test only(2)

1010 = Internal test only(2)

1001 = Full speed divided by 512

1000 = Full speed divided by 256

0111 = Full speed divided by 128

0110 = Full speed divided by 64

0101 = Full speed divided by 32

0100 = Full speed divided by 16

0011 = Full speed divided by 8

0010 = Full speed divided by 4

0001 = Full speed divided by 2

0000 = Full-speed rate (Default)

bit 3-0

OUT_CLKRATE<3:0>: Output clock rate control bits(3,4)

1111 = Full-speed rate

1110 = No clock output

1101 = No clock output

1100 = No clock output

1011 = No clock output

1010 = No clock output

1001 = Full speed divided by 512

1000 = Full speed divided by 256

0111 = Full speed divided by 128

0110 = Full speed divided by 64

0101 = Full speed divided by 32

0100 = Full speed divided by 16

0011 = Full speed divided by 8

0010 = Full speed divided by 4

0001 = Full speed divided by 2

0000 = No clock output (Default)

Note

This register should be used to realign the output data and clock when the decimation or digital down-conversion (DDC) option

is used.

1100 - 1010: Do not reprogram. These settings are used for the internal test only. If these bits are reprogrammed with differ-

ent settings, the outputs will be in an undefined state.

Bits <3:0> become active if EN_DATCLK_IND = 1 in Address 0x01 (Register 5-2).

When no clock output is selected (Bits 1110 - 1010): clock output is not available at the DCLK+/DCLK- pins.

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