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MCP37D11-80E/TE Datasheet(PDF) 75 Page - Microchip Technology |
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MCP37D11-80E/TE Datasheet(HTML) 75 Page - Microchip Technology |
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75 / 136 page  0x85 Numerically Controlled Oscillator (NCO) Tuning - Upper Byte NCO_TUNE<31:24> 0x00 0x86 CH0 NCO Phase Offset in CW or DDC Mode - Lower Byte CH0_NCO_PHASE<7:0> 0x00 0x87 CH0 NCO Phase Offset in CW or DDC Mode - Upper Byte CH0_NCO_PHASE<15:8> 0x00 0x88 CH1 NCO Phase Offset in CW or DDC Mode - Lower Byte CH1_NCO_PHASE<7:0> 0x00 0x89 CH1 NCO Phase Offset in CW or DDC Mode - Upper Byte CH1_NCO_PHASE<15:8> 0x00 0x8A CH2 NCO Phase Offset in CW or DDC Mode - Lower Byte CH2_NCO_PHASE<7:0> 0x00 0x8B CH2 NCO Phase Offset in CW or DDC Mode - Upper Byte CH2_NCO_PHASE<15:8> 0x00 0x8C CH3 NCO Phase Offset in CW or DDC Mode - Lower Byte CH3_NCO_PHASE<7:0> 0x00 0x8D CH3 NCO Phase Offset in CW or DDC Mode - Upper Byte CH3_NCO_PHASE<15:8> 0x00 0x8E CH4 NCO Phase Offset in CW or DDC Mode - Lower Byte CH4_NCO_PHASE<7:0> 0x00 0x8F CH4 NCO Phase Offset in CW or DDC Mode - Upper Byte CH4_NCO_PHASE<15:8> 0x00 0x90 CH5 NCO Phase Offset in CW or DDC Mode - Lower Byte CH5_NCO_PHASE<7:0> 0x00 0x91 CH5 NCO Phase Offset in CW or DDC Mode - Upper Byte CH5_NCO_PHASE<15:8> 0x00 0x92 CH6 NCO Phase Offset in CW or DDC Mode - Lower Byte CH6_NCO_PHASE<7:0> 0x00 0x93 CH6 NCO Phase Offset in CW or DDC Mode - Upper Byte CH6_NCO_PHASE<15:8> 0x00 0x94 CH7 NCO Phase Offset in CW or DDC Mode - Lower Byte CH7_NCO_PHASE<7:0> 0x00 0x95 CH7 NCO Phase Offset in CW or DDC Mode - Upper Byte CH7_NCO_PHASE<15:8> 0x00 0x96 CH0 Digital Gain CH0_DIG_GAIN<7:0> 0x3C 0x97 CH1 Digital Gain CH1_DIG_GAIN<7:0> 0x3C 0x98 CH2 Digital Gain CH2_DIG_GAIN<7:0> 0x3C 0x99 CH3 Digital Gain CH3_DIG_GAIN<7:0> 0x3C TABLE 5-3: REGISTER MAP TABLE (CONTINUED) Addr. Register Name Bits Default Value b7 b6 b5 b4 b3 b2 b1 b0 Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled Bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown 2: Read-only register. Preprogrammed at the factory for internal use. |
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